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? 2001 microchip technology inc. advance information ds39541a-page 1 PIC18C601/801 high performance risc cpu: ? c compiler optimized architecture instruction set linear program memory addressing up to 2 mbytes linear data memory addressing to 4 kbytes up to 160 ns instruction cycle: - dc - 25 mhz clock input - 4 mhz - 6 mhz clock input with pll active 16-bit wide instructions, 8-bit wide data path priority levels for interrupts 8 x 8 single cycle hardware multiplier peripheral features: high current sink/source 25 ma/25 ma up to 47 i/o pins with individual direction control three external interrupt pins timer0 module: 8-bit/16-bit timer/counter with 8-bit programmable prescaler timer1 module: 16-bit timer/counter (time-base for ccp) timer2 module: 8-bit timer/counter with 8-bit period register timer3 module: 16-bit timer/counter secondary oscillator clock option - timer1/timer3 two capture/compare/pwm (ccp) modules ccp pins can be configured as: - capture input: 16-bit, max. resolution 10 ns - compare is 16-bit, max. resolution 160 ns (t cy ) - pwm output: pwm resolution is 1- to 10-bit max. pwm freq. @: 8-bit resolution = 99 khz 10-bit resolution = 24.4 khz master synchronous serial port (mssp) with two modes of operation: - 3-wire spi? (supports all 4 spi modes) -i 2 c? master and slave mode addressable usart module: supports interrupt on address bit advanced analog features: 10-bit analog-to-digital converter module (a/d) with: - fast sampling rate - conversion available during sleep - dnl = 1 lsb, inl = 1 lsb - up to 12 channels available programmable low voltage detection (lvd) module - supports interrupt on low voltage detection special microcontroller features: power-on reset (por), power-up timer (pwrt), and oscillator start-up timer (ost) watchdog timer (wdt) with its own on-chip rc oscillator on-chip boot ram for boot loader application 8-bit or 16-bit external memory interface modes up to two software programmable chip select sig- nals (cs1 and cs2 ) one programmable chip i/o select signal (csio ) for memory mapped i/o expansion power saving sleep mode different oscillator options, including: - 4x phase lock loop (of primary oscillator) - secondary oscillator (32 khz) clock input cmos technology: low power, high speed cmos technology fully static design wide operating voltage range (2.0v to 5.5v) industrial and extended temperature ranges low power consumption device external program memory on-chip ram (bytes) on-chip maximum addressing (bytes) maximum single word instructions PIC18C601 256k 128k 1.5k pic18c801 2m 1m 1.5k high-performance rom-less microcontrollers with external memory bus
PIC18C601/801 ds39541a-page 2 advance information ? 2001 microchip technology inc. pin diagrams 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 re2/ad10 re3/ad11 re4/ad12 re5/ad13 re6/ad14 re7/ad15 rd0/ad0 v dd v ss rd1/ad1 rd2/ad2 rd3/ad3 rd4/ad4 rd5/ad5 rd6/ad6 rd7/ad7 re1/ad9 re0/ad8 rg0/ale rg1/oe rg2/wrl rg3/wrh mclr /v pp rg4/ba0 v ss v dd rf7/ub rf6/lb rf5/cs1 rf4/a16 rf3/csio rf2/an7 rb0/int0 rb1/int1 rb2/int2 rb3/ccp2 rb4 rb5 rb6 v ss osc2/clko osc1/clki v dd rb7 rc4/sdi/sda rc3/sck/scl rc2/ccp1 rf0/an5 rf1/an6 av dd av ss ra3/an3/v ref + ra2/an2/v ref - ra1/an1 ra0/an0 v ss v dd ra4/t0cki ra5/ss /an4/lvdin rc1/t1osi rc0/t1oso/t13cki rc7/rx/dt rc6/tx/ck rc5/sdo 64-pin tqfp PIC18C601
? 2001 microchip technology inc. advance information ds39541a-page 3 PIC18C601/801 pin diagrams (cont.?d) 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 9 8 7 6 5 4 3 2 1 6867666564636261 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 rb0/int0 rb1/int1 rb2/int2 rb3/ccp2 rb4 rb5 rb6 v ss nc osc1/clki v dd rb7 rc4/sdi/sda rc3/sck/scl rc2/ccp1 re1/ad9 re0/ad8 rg0/ale rg1/oe rg2/wrl rg3/wrh mclr /v pp rg4/ba0 v ss v dd rf7/ub rf6/lb rf5/cs1 rf4/a16 rf3/csio rf2/an7 re2/ad10 re3/ad11 re4/ad12 re5/ad13 re6/ad14 re7/ad15 rd0/ad0 v dd v ss rd1/ad1 rd2/ad2 rd3/ad3 rd4/ad4 rd5/ad5 rd6/ad6 rd7/ad7 rf1/an6 rf0/an5 av dd av ss ra3/an3/v ref + ra2/an2/v ref - ra1/an1 ra0/an0 v dd ra4/t0cki ra5/ss /an4/lvdin rc1/t1osi rc0/t1oso/t13cki rc7/rx/dt rc6/tx/ck rc5/sdo osc2/clko nc nc nc v ss 68-pin plcc pic18c6 01
PIC18C601/801 ds39541a-page 4 advance information ? 2001 microchip technology inc. pin diagrams (cont. ? d) 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 64 63 62 61 21 22 23 24 25 26 27 28 29 30 31 32 re2/ad10 re3/ad11 re4/ad12 re5/ad13 re6/ad14 re7/ad15 rd0/ad0 v dd v ss rd1/ad1 rd2/ad2 rd3/ad3 rd4/ad4 rd5/ad5 rd6/ad6 rd7/ad7 re1/ad9 re0/ad8 rg0/ale rg1/oe rg2/wrl rg3/wrh mclr /v pp rg4/ba0 v ss v dd rf7/ub rf6/lb rf5/cs1 rf4/cs2 rf3/csio rf2/an7 rb0/int0 rb1/int1 rb2/int2 rb3/ccp2 rb4 rb5 rb6 v ss osc2/clko osc1/clki v dd rb7 rc4/sdi/sda rc3/sck/scl rc2/ccp1 rf0/an5 rf1/an6 av dd av ss ra3/an3/v ref + ra2/an2/v ref - ra1/an1 ra0/an0 v ss v dd ra4/t0cki ra5/ss /an4/lvdin rc1/t1osi rc0/t1oso/t13cki rc7/rx/dt rc6/tx/ck rc5/sdo rj0/d7 rj1/d6 rh1/a17 rh0/a16 1 2 rh2/a18 rh3/a19 17 18 rh4/an8 rh5/an9 rh6/an10 rh7/an11 rj1/d1 rj0/d0 37 rj3/d3 rj2/d2 50 49 rj5/d5 rj4/d4 19 20 33 34 35 36 38 58 57 56 55 54 53 52 51 60 59 68 67 66 65 72 71 70 69 74 73 78 77 76 75 79 80 80-pin tqfp pic18c801
? 2001 microchip technology inc. advance information ds39541a-page 5 PIC18C601/801 pin diagrams (cont. ? d) 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 9876 54321 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 rb0/int0 rb1/int1 rb2/int2 rb3/ccp2 rb4 rb5 rb6 v ss nc osc1/clki v dd rb7 rc4/sdi/sda rc3/sck/scl rc2/ccp1 re1/ad9 re0/ad8 rg0/ale rg1/oe rg2/wrl rg3/wrh mclr /v pp rg4/ba0 v ss v dd rf7/ub rf6/lb rf5/cs1 rf4/cs2 rf3/csio rf2/an7 re2/ad10 re3/ad11 re4/ad12 re5/ad13 re6/ad14 re7/ad15 rd0/ad0 v dd v ss rd1/ad1 rd2/ad2 rd3/ad3 rd4/ad4 rd5/ad5 rd6/ad6 rd7/ad7 rf1/an6 rf0/an5 av dd av ss ra3/an3/v ref + ra2/an2/v ref - ra1/an1 ra0/an0 v ss v dd ra4/t0cki ra5/ss /an4/lvdin rc1/t1osi rc0/t1oso/t13cki rc7/rx/dt rc6/tx/ck rc5/sdo rj5/d5 rj4/d4 rj7/d7 rj6/d6 rj0/d0 rj1/d1 rj3/d3 rj2/d2 rh1/a17 rh0/a16 rh2/a18 rh3/a19 rh6/an10 rh7/an11 rh4/an8 rh5/an9 67 66 65 64 63 62 61 68 74 73 72 71 70 76 79 78 77 80 83 82 81 84 75 69 osc2/clko nc nc nc 84-pin plcc pic18c801
PIC18C601/801 ds39541a-page 6 advance information ? 2001 microchip technology inc. table of contents 1.0 device overview............................................................................................................. ..................................... 9 2.0 oscillator configurations................................................................................................... ................................. 21 3.0 reset....................................................................................................................... ........................................ 29 4.0 memory organization ......................................................................................................... ............................... 39 5.0 external memory interface................................................................................................... .............................. 63 6.0 table reads/table writes .................................................................................................... ............................. 73 7.0 8 x 8 hardware multiplier ................................................................................................... ............................... 85 8.0 interrupts.................................................................................................................. .......................................... 89 9.0 i/o ports................................................................................................................... ........................................ 103 10.0 timer0 module.............................................................................................................. ................................... 127 11.0 timer1 module.............................................................................................................. ................................... 130 12.0 timer2 module.............................................................................................................. ................................... 135 13.0 timer3 module.............................................................................................................. ................................... 137 14.0 capture/compare/pwm (ccp) modules.......................................................................................... ............... 141 15.0 master synchronous serial port (mssp) module............................................................................... ............. 149 16.0 addressable universal synchronous asynchronous receiver transmitter (usart) ..................................... 177 17.0 10-bit analog-to-digital converter (a/d) module ............................................................................ ................. 193 18.0 low voltage detect......................................................................................................... ................................. 203 19.0 special features of the cpu ................................................................................................ ........................... 207 20.0 instruction set summary .................................................................................................... ............................. 215 21.0 development support ........................................................................................................ .............................. 259 22.0 electrical characteristics ................................................................................................. ................................ 265 23.0 dc and ac characteristics graphs and tables ................................................................................ .............. 295 24.0 packaging information ...................................................................................................... ............................... 297 appendix a: data sheet revision history......................................................................................... ......................... 303 appendix b: device differences .................................................................................................. .............................. 303 appendix c: device migrations ................................................................................................... ............................... 304 appendix d: migrating from other picmicro devices ............................................................................... .................. 304 appendix e: development tool version requirements ............................................................................... .............. 305 index .......................................................................................................................... ................................................. 307 on-line support ................................................................................................................ .......................................... 315 reader response ................................................................................................................ ....................................... 316 product identification system.................................................................................................. .................................... 317
? 2001 microchip technology inc. advance information ds39541a-page 7 PIC18C601/801 to our valued customers it is our intention to provide our valued customers with the best documentation possible to ensure successful use of your micro chip products. to this end, we will continue to improve our publications to better suit your needs. our publications will be refined and enhanced as new volumes and updates are introduced. if you have any questions or comments regarding this publication, please contact the marketing communications department via e-mail at docerrors@mail.microchip.com or fax the reader response form in the back of this data sheet to (480) 792-4150. we welcome your feedback. most current data sheet to obtain the most up-to-date version of this data sheet, please register at our worldwide web site at: http://www.microchip.com you can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page . the last character of the literature number is the version number, (e.g., ds30000a is version a of document ds30000). errata an errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for curren t devices. as device/documentation issues become known to us, we will publish an errata sheet. the errata will specify the revisi on of silicon and revision of document to which it applies. to determine if an errata sheet exists for a particular device, please check with one of the following: microchip ? s worldwide web site; http://www.microchip.com your local microchip sales office (see last page) the microchip corporate literature center; u.s. fax: (480) 792-7277 when contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (inclu de liter- ature number) you are using. customer notification system register on our web site at www.microchip.com/cn to receive the most current information on all of our products.
PIC18C601/801 ds39541a-page 8 advance information ? 2001 microchip technology inc. notes:
? 2001 microchip technology inc. advance information ds39541a-page 9 PIC18C601/801 1.0 device overview this document contains device specific information for the following two devices: 1. PIC18C601 2. pic18c801 the PIC18C601 is available in 64-pin tqfp and 68-pin plcc packages. the pic18c801 is available in 80-pin tqfp and 84-pin plcc packages. an overview of features is shown in table 1-1. device block diagrams are provided in figure 1-1 for the 64/68-pin configuration, and figure 1-2 for the 80/ 84-pin configuration. the pinouts for both packages are listed in table 1-2. table 1-1: device features features PIC18C601 pic18c801 operating frequency dc - 25 mhz dc - 25 mhz external program memory bytes 256k 2m max. # of single word instructions 128k 1m data memory (bytes) 1536 1536 interrupt sources 15 15 i/o ports ports a - g ports a - h, j timers 4 4 capture/compare/pwm modules 2 2 serial communications mssp, addressable usart mssp, addressable usart 10-bit analog-to-digital module 8 input channels 12 input channels resets (and delays) por, reset instruction, stack full, stack underflow (pwrt, ost) por, reset instruction, stack full, stack underflow (pwrt, ost) programmable low voltage detect yes yes 8-bit external memory interface yes yes 8-bit de-multiplexed external memory interface no yes 16-bit external memory interfaces yes yes on-chip chip select signals cs1 cs1 , cs2 on-chip i/o chip select signal yes yes instruction set 75 instructions 75 instructions packages 64-pin tqfp 68-pin plcc 80-pin tqfp 84-pin plcc
PIC18C601/801 ds39541a-page 10 advance information ? 2001 microchip technology inc. figure 1-1: PIC18C601 block diagram instruction decode & control osc1/clki osc2/clko mclr v dd , v ss porta portb portc ra4/t0cki ra5/an4/ss /lvdin rb0/int0 rc0/t1oso/t13cki rc1/t1osi rc2/ccp1 rc3/sck/scl rc4/sdi/sda rc5/sdo rc6/tx1/ck1 rc7/rx1/dt1 usart1 ccp1 synchronous timer0 timer1 timer2 serial port ra3/an3/v ref + ra2/an2/v ref - ra1/an1 ra0/an0 timing generation rb1/int1 address<12> 12 bsr fsr0 fsr1 fsr2 inc/dec logic 4 12 4 pch pcl pclath 8 31 level stack program counter prodl prodh 8 x 8 multiply wreg 8 bitop 8 8 alu<8> 8 address latch program memory (up to 256 kbytes) data latch 20 21 21 16 8 8 8 table pointer<21> inc/dec logic 21 8 data bus<8> table latch 8 ir 12 3 rom latch timer3 portd rd7:rd0/ad7:ad0 ccp2 rb2/int2 rb3/ccp2 t1osi t1oso pclatu pcu portf rf0/an5 rf1/an6 rf2/an7 portg 10-bit a/d rb4 rb5 rb6 rb7 re7:re0/ad15:ad8 porte rf3/csio rf4/a16 rf5/cs1 rf6/lb rf7/ub rg0/ale rg1/oe rg2/wrl rg3/wrh rg4/ba0 ad7:ad0 a16, ad15:ad8 system bus interface power-up timer oscillator start-up timer power-on reset watchdog timer low voltage detect decode bank0,f data latch data ram 1 kbyte address latch 5
? 2001 microchip technology inc. advance information ds39541a-page 11 PIC18C601/801 figure 1-2: pic18c801 block diagram instruction decode & control osc1/clki osc2/clko mclr v dd , v ss porta portb portc ra4/t0cki ra5/an4/ss /lvdin rb0/int0 rc0/t1oso/t13cki rc1/t1osi rc2/ccp1 rc3/sck/scl rc4/sdi/sda rc5/sdo rc6/tx1/ck1 rc7/rx1/dt1 usart1 ccp1 synchronous timer0 timer1 timer2 serial port ra3/an3/v ref + ra2/an2/v ref - ra1/an1 ra0/an0 timing generation rb1/int1 data latch data ram address<12> 12 bank0,f fsr0 fsr1 fsr2 inc/dec logic decode 4 12 4 pch pcl pclath 8 31 level stack program counter prodl prodh 8 x 8 multiply wreg 8 bitop 8 8 alu<8> 8 address latch program memory (up to 2 mbytes) data latch 20 21 21 16 8 8 8 table pointer<21> inc/dec logic 21 8 data bus<8> table latch 8 ir 12 3 rom latch timer3 portd rd7:rd0/ad7:ad0 ccp2 rb2/int2 rb3/ccp2 t1osi t1oso pclatu pcu portf rf0/an5 rf1/an6 rf2/an7 portg 10-bit a/d rb4 rb5 rb6 rb7 re7:re0/ad15:ad8 porte rf3/csio rf4/cs2 rf5/cs1 rf6/lb rf7/ub rg0/ale rg1/oe rg2/wrl rg3/wrh rg4/ba0 porth rh3:rh0/a19:a16 portj rj7:rj0/d7:d0 rh4/an8 rh5/an9 rh6/an10 rh7/an11 ad7:ad0 a19:a16, ad15:ad0 system bus interface 5 power-up timer oscillator start-up timer power-on reset watchdog timer low voltage detect 1 kbyte address latch bsr
PIC18C601/801 ds39541a-page 12 advance information ? 2001 microchip technology inc. table 1-2: pinout i/o descriptions pin name pin number pin type buffer type PIC18C601 pic18c801 tqfp plcc tqfp plcc description mclr /v pp mclr v pp 716920 i p st master clear (reset) input. this pin is an active low reset to the device. programming voltage input. nc ? 1, 18, 35, 52 ? 1, 22, 43, 64 ?? these pins should be left unconnected. osc1/clki osc1 clki 39 50 49 62 i i cmos/st cmos oscillator crystal input or external clock source input. st buffer when in rc mode. otherwise cmos. external clock source input. always associated with pin function osc1 (see osc1/clki, osc2/clko pins). osc2/clko osc2 clko 40 51 50 63 o o ? ? oscillator crystal output. connects to crystal or resonator in crystal oscillator mode. in rc mode, osc2 pin outputs clko, which has 1/4 the frequency of osc1 and denotes the instruction cycle rate. legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p = power od = open drain (no p diode to v dd )
? 2001 microchip technology inc. advance information ds39541a-page 13 PIC18C601/801 porta is a bi-directional i/o port. ra0/an0 ra0 an0 24 34 30 42 i/o i ttl analog digital i/o. analog input 0. ra1/an1 ra1 an1 23 33 29 41 i/o i ttl analog digital i/o. analog input 1. ra2/an2/v ref - ra2 an2 v ref - 22 32 28 40 i/o i i ttl analog analog digital i/o. analog input 2. a/d reference voltage (low) input. ra3/an3/v ref + ra3 an3 v ref + 21 31 27 39 i/o i i ttl analog analog digital i/o. analog input 3. a/d reference voltage (high) input. ra4/t0cki ra4 t0cki 28 39 34 47 i/o i st/od st digital i/o ? open drain when configured as output. timer0 external clock input. ra5/an4/ss /lvdin ra5 an4 ss lvdin 27 38 33 46 i/o i i i ttl analog st analog digital i/o. analog input 4. spi slave select input. low voltage detect input. table 1-2: pinout i/o descriptions (continued) pin name pin number pin type buffer type PIC18C601 pic18c801 tqfp plcc tqfp plcc description legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p = power od = open drain (no p diode to v dd )
PIC18C601/801 ds39541a-page 14 advance information ? 2001 microchip technology inc. portb is a bi-directional i/o port. portb can be software programmed for internal weak pull-ups on all inputs. rb0/int0 rb0 int0 48 60 58 72 i/o i ttl st digital i/o. external interrupt 0. rb1/int1 rb1 int1 47 59 57 71 i/o i ttl st digital i/o. external interrupt 1. rb2/int2 rb2 int2 46 58 56 70 i/o i ttl st digital i/o. external interrupt 2. rb3/ccp2 rb3 ccp2 45 57 55 69 i/o i/o ttl st digital i/o. capture2 input, compare2 output, pwm2 output. rb4 44 56 54 68 i/o ttl digital i/o, interrupt-on-change pin. rb5 43 55 53 67 i/o ttl digital i/o, interrupt-on-change pin. rb6 42545266i/o i ttl st digital i/o, interrupt-on-change pin. icsp programming clock. rb7 37484760i/o i/o ttl st digital i/o, interrupt-on-change pin. icsp programming data. table 1-2: pinout i/o descriptions (continued) pin name pin number pin type buffer type PIC18C601 pic18c801 tqfp plcc tqfp plcc description legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p = power od = open drain (no p diode to v dd )
? 2001 microchip technology inc. advance information ds39541a-page 15 PIC18C601/801 portc is a bi-directional i/o port. rc0/t1oso/t13cki rc0 t1oso t13cki 30 41 36 49 i/o o i st ? st digital i/o. timer1 oscillator output. timer1/timer3 external clock input. rc1/t1osi rc1 t1osi 29 40 35 48 i/o i st cmos digital i/o. timer1 oscillator input. rc2/ccp1 rc2 ccp1 33 44 43 56 i/o i/o st st digital i/o. capture1 input/compare1 output/pwm1 output. rc3/sck/scl rc3 sck scl 34 45 44 57 i/o i/o i/o st st st digital i/o. synchronous serial clock input/output for spi mode. synchronous serial clock input/output for i 2 c mode. rc4/sdi/sda rc4 sdi sda 35 46 45 58 i/o i i/o st st st digital i/o. spi data in. i 2 c data i/o. rc5/sdo rc5 sdo 36 47 46 59 i/o o st ? digital i/o. spi data out. rc6/tx/ck rc6 tx ck 31 42 37 50 i/o o i/o st ? st digital i/o. usart asynchronous transmit. usart synchronous clock. rc7/rx/dt rc7 rx dt 32 43 38 51 i/o i i/o st st st digital i/o. usart asynchronous receive. usart synchronous data. table 1-2: pinout i/o descriptions (continued) pin name pin number pin type buffer type PIC18C601 pic18c801 tqfp plcc tqfp plcc description legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p = power od = open drain (no p diode to v dd )
PIC18C601/801 ds39541a-page 16 advance information ? 2001 microchip technology inc. portd is a bi-directional i/o port. these pins have ttl input buffers when external memory is enabled. rd0/ad0 rd0 ad0 583723 i/o i/o st ttl digital i/o. external memory address/data 0. rd1/ad1 rd1 ad1 55 67 69 83 i/o i/o st ttl digital i/o. external memory address/data 1. rd2/ad2 rd2 ad2 54 66 68 82 i/o i/o st ttl digital i/o. external memory address/data 2. rd3/ad3 rd3 ad3 53 65 67 81 i/o i/o st ttl digital i/o. external memory address/data 3. rd4/ad4 rd4 ad4 52 64 66 80 i/o i/o st ttl digital i/o. external memory address/data 4. rd5/ad5 rd5 ad5 51 63 65 79 i/o i/o st ttl digital i/o. external memory address/data 5. rd6/ad6 rd6 ad6 50 62 64 78 i/o i/o st ttl digital i/o. external memory address/data 6. rd7/ad7 rd7 ad7 49 61 63 77 i/o i/o st ttl digital i/o. external memory address/data 7. table 1-2: pinout i/o descriptions (continued) pin name pin number pin type buffer type PIC18C601 pic18c801 tqfp plcc tqfp plcc description legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p = power od = open drain (no p diode to v dd )
? 2001 microchip technology inc. advance information ds39541a-page 17 PIC18C601/801 porte is a bi-directional i/o port. re0/ad8 re0 ad8 211415 i/o i/o st ttl digital i/o. external memory address/data 8. re1/ad9 re1 ad9 110314 i/o i/o st ttl digital i/o. external memory address/data 9. re2/ad10 re2 ad10 649789 i/o i/o st ttl digital i/o. external memory address/data 10. re3/ad11 re3 ad11 638778 i/o i/o st ttl digital i/o. external memory address/data 11. re4/ad12 re4 ad12 627767 i/o i/o st ttl digital i/o. external memory address/data 12. re5/ad13 re5 ad13 616756 i/o i/o st ttl digital i/o. external memory address/data 13. re6/ad14 re6 ad14 605745 i/o i/o st ttl digital i/o. external memory address/data 14. re7/ad15 re7 ad15 594734 i/o i/o st st digital i/o. external memory address/data 15. table 1-2: pinout i/o descriptions (continued) pin name pin number pin type buffer type PIC18C601 pic18c801 tqfp plcc tqfp plcc description legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p = power od = open drain (no p diode to v dd )
PIC18C601/801 ds39541a-page 18 advance information ? 2001 microchip technology inc. portf is a bi-directional i/o port. rf0/an5 rf0 an5 18 28 24 36 i/o i st analog digital i/o. analog input 5. rf1/an6 rf1 an6 17 27 23 35 i/o i st analog digital i/o. analog input 6. rf2/an7 rf2 an7 16 26 18 30 i/o i st analog digital i/o. analog input 7. rf3/csio rf3 csio 15 25 17 29 i/o i/o st st digital i/o. system bus chip select i/o. rf4/a16 rf4/cs2 rf4 a16 cs2 14 ? 24 ? ? 16 ? 28 i/o i/o o st ttl ttl digital i/o. external memory address 16. chip select 2. rf5/cs1 rf5 cs1 13 23 15 27 i/o o st ttl digital i/o. chip select 1. rf6/lb rf6 lb 12 22 14 26 i/o o st ttl digital i/o. low byte select signal for external memory interface. rf7/ub rf7 ub 11 21 13 25 i/o o st ttl digital i/o. high byte select signal for external memory interface. table 1-2: pinout i/o descriptions (continued) pin name pin number pin type buffer type PIC18C601 pic18c801 tqfp plcc tqfp plcc description legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p = power od = open drain (no p diode to v dd )
? 2001 microchip technology inc. advance information ds39541a-page 19 PIC18C601/801 portg is a bi-directional i/o port. rg0/ale rg0 ale 312516 i/o o st ttl digital i/o. address latch enable. rg1/oe rg1 oe 413617 i/o o st ttl digital i/o. output enable. rg2/wrl rg2 wrl 514718 i/o o st ttl digital i/o. write low control. rg3/wrh rg3 wrh 615819 i/o o st ttl digital i/o. write high control. rg4/ba0 rg4 ba0 8 171021 i/o o st ttl digital i/o. system bus byte address 0. porth is a bi-directional i/o port. rh0/a16 rh0 a16 ?? 79 10 i/o o st ttl digital i/o. external memory address 16. rh1/a17 rh1 a17 ?? 80 11 i/o o st ? digital i/o. external memory address 17. rh2/a18 rh2 a18 ?? 112 i/o o st ? digital i/o. external memory address 18. rh3/a19 rh3 a19 ?? 213 i/o o st ? digital i/o. external memory address 19. rh4/an8 rh4 an8 ?? 19 31 i/o i st analog digital i/o. analog input 8. rh5/an9 rh5 an9 ?? 20 32 i/o i st analog digital i/o. analog input 9. rh6/an10 rh6 an10 ?? 21 33 i/o i st analog digital i/o. analog input 10. rh7/an11 rh7 an11 ?? 22 34 i/o i st analog digital i/o. analog input 11. table 1-2: pinout i/o descriptions (continued) pin name pin number pin type buffer type PIC18C601 pic18c801 tqfp plcc tqfp plcc description legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p = power od = open drain (no p diode to v dd )
PIC18C601/801 ds39541a-page 20 advance information ? 2001 microchip technology inc. portj is a bi-directional i/o port. rj0/d0 rj0 d0 ?? 39 52 i/o i/o st ttl digital i/o. system bus data bit 0. rj1/d1 rj1 d1 ?? 40 53 i/o i/o st ttl digital i/o. system bus data bit 1. rj2/d2 rj2 d2 ?? 41 54 i/o i/o st ttl digital i/o. system bus data bit 2. rj3/d3 rj3 d3 ?? 42 55 i/o i/o st ttl digital i/o. system bus data bit 3. rj4/d4 rj4 d4 ?? 59 73 i/o i/o st ttl digital i/o. system bus data bit 4. rj5/d5 rj5 d5 ?? 60 74 i/o i/o st ttl digital i/o. system bus data bit 5. rj6/d6 rj6 d6 ?? 61 75 i/o i/o st ttl digital i/o. system bus data bit 6. rj7/d7 rj7 d7 ?? 62 76 i/o i/o st ttl digital i/o. system bus data bit 7. v ss 9, 25, 41, 56 19, 36, 53, 68 11,31, 51, 70 23, 44, 65, 84 p ? ground reference for logic and i/o pins. v dd 10,26, 38, 57 2, 20, 37, 49 12,32, 48, 71 2, 24, 45, 61 p ? positive supply for logic and i/o pins. a vss 20 30 26 38 p ? ground reference for analog modules. a vdd 19 29 25 37 p ? positive supply for analog modules. table 1-2: pinout i/o descriptions (continued) pin name pin number pin type buffer type PIC18C601 pic18c801 tqfp plcc tqfp plcc description legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p = power od = open drain (no p diode to v dd )
? 2001 microchip technology inc. advance information ds39541a-page 21 PIC18C601/801 2.0 oscillator configurations 2.1 oscillator types PIC18C601/801 can be operated in one of four oscilla- tor modes, programmable by configuration bits fosc1:fosc0 in config1h register: 1. lp low power crystal 2. hs high speed crystal/resonator 3. rc external resistor/capacitor 4. ec external clock 2.2 crystal oscillator/ceramic resonators in lp or hs oscillator modes, a crystal or ceramic res- onator is connected to the osc1 and osc2 pins to establish oscillation. figure 2-1 shows the pin connec- tions. an external clock source may also be connected to the osc1 pin, as shown in figure 2-3 and figure 2-4. PIC18C601/801 oscillator design requires the use of a parallel cut crystal. figure 2-1: crystal/ceramic resonator operation (hs or lp osc configuration) note: use of a series cut crystal may give a fre- quency out of the crystal manufacturer ? s specifications. note 1: see table 2-1 and table 2-2 for recom- mended values of c1 and c2. 2: a series resistor (r s ) may be required for at strip cut crystals. 3: r f varies with the crystal chosen. c1 (1) c2 (1) xtal osc2 osc1 r f (3) sleep to logic PIC18C601/801 r s (2) internal
PIC18C601/801 ds39541a-page 22 advance information ? 2001 microchip technology inc. table 2-1: ceramic resonators table 2-2: capacitor selection for crystal oscillator 2.3 rc oscillator for timing insensitive applications, the "rc" oscillator mode offers additional cost savings. the rc oscillator frequency is a function of the supply voltage, the resis- tor (r ext ) and capacitor (c ext ) values and the operat- ing temperature. in addition to this, the oscillator frequency will vary from unit to unit due to normal pro- cess parameter variation. furthermore, the difference in lead frame capacitance between package types will also affect the oscillation frequency, especially for low c ext values. the user also needs to take into account variation due to tolerance of external r and c compo- nents used. figure 2-2 shows how the rc combination is connected. in the rc oscillator mode, the oscillator frequency divided by 4 is available on the osc2 pin. this signal may be used for test purposes or to synchronize other logic. figure 2-2: rc oscillator mode ranges tested: mode freq. osc1 osc2 hs 8.0 mhz 16.0 mhz 20.0 mhz 25.0 mhz 10 - 68 pf 10 - 22 pf tbd tbd 10 - 68 pf 10 - 22 pf tbd tbd hs+pll 4.0 mhz tbd tbd these values are for design guidance only. see notes on this page. resonators used: 4.0 mhz murata erie csa4.00mg 0.5% 8.0 mhz murata erie csa8.00mt 0.5% 16.0 mhz murata erie csa16.00mx 0.5% all resonators used did not have built-in capacitors. osc type crystal freq. cap. range c1 cap. range c2 lp 32.0 khz 33 pf 33 pf 200 khz 15 pf 15 pf hs 4.0 mhz 15 pf 15 pf 8.0 mhz 15-33 pf 15-33 pf 20.0 mhz 15-33 pf 15-33 pf 25.0 mhz tbd tbd hs+pll 4.0 mhz 15 pf 15 pf these values are for design guidance only. see notes on this page. crystals used 32.0 khz epson c-001r32.768k-a 20 ppm 200 khz std xtl 200.000khz 20 ppm 1.0 mhz ecs ecs-10-13-1 50 ppm 4.0 mhz ecs ecs-40-20-1 50 ppm 8.0 mhz epson ca-301 8.000m-c 30 ppm 20.0 mhz epson ca-301 20.000m-c 30 ppm note 1: recommended values of c1 and c2 are identical to the ranges tested (table 2-1). 2: higher capacitance increases the stability of the oscillator, but also increases the start-up time. 3: since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appro- priate values of external components. 4: rs may be required in hs mode to avoid overdriving crystals with low drive level specification. osc2/clko c ext r ext osc1 f osc /4 internal clock v dd v ss recommended values: 3 k ? r ext 100 k ? c ext > 20pf or i/o PIC18C601/801
? 2001 microchip technology inc. advance information ds39541a-page 23 PIC18C601/801 2.4 external clock input the ec oscillator mode requires an external clock source to be connected to the osc1 pin. the feedback device between osc1 and osc2 is turned off in these modes to save current. there is no oscillator start-up time required after a power-on reset or after a recovery from sleep mode. in the ec oscillator mode, the oscillator frequency divided by 4 is available on the osc2 pin. this signal may be used for test purposes or to synchronize other logic. figure 2-3 shows the pin connections for the ec oscillator mode. figure 2-3: external clock input operation (ec osc configuration) 2.5 hs4 (pll) a phase lock loop (pll) circuit is provided as a soft- ware programmable option for users that want to multi- ply the frequency of the incoming crystal oscillator signal by 4. for an input clock frequency of 6 mhz, the internal clock frequency will be multiplied to 24 mhz. this is useful for customers who are concerned with emi due to high frequency crystals. the pll is enabled by configuring hs oscillator mode and setting the pllen bit in the oscon register. if hs oscillator mode is not selected, or pllen bit in osccon register is clear, the pll is not enabled and the system clock will come directly from osc1. hs oscillator mode is the default for PIC18C601/801. in all other modes, the pllen bit and the scs1 bit are forced to ? 0 ? . a pll lock timer is used to ensure that the pll has locked before device execution starts. the pll lock timer has a time-out, referred to as t pll . figure 2-4: pll block diagram osc1 osc2 f osc /4 clock from ext. system PIC18C601/801 mux vco loop filter feedback divider 3210 crystal osc oscout oscin pll enable f in f out sysclk phase comparator c vco hs osc
PIC18C601/801 ds39541a-page 24 advance information ? 2001 microchip technology inc. 2.6 oscillator switching feature PIC18C601/801 devices include a feature that allows the system clock source to be switched from the main oscillator to an alternate low frequency clock source. for PIC18C601/801 devices, this alternate clock source is the timer1 oscillator. if a low frequency crys- tal (32 khz, for example) has been attached to the timer1 oscillator pins and the timer1 oscillator has been enabled, the device can switch to a low power execution mode. figure 2-5 shows a block diagram of the system clock sources. 2.6.1 system clock switch bit the system clock source switching is performed under software control. the system clock switch bit, scs0 (osccon register), controls the clock switching. when the scs0 bit is ? 0 ? , the system clock source comes from the main oscillator, selected by the fosc2:fosc0 con- figuration bits in config1h register. when the scs0 bit is set, the system clock source will come from the timer1 oscillator. the scs0 bit is cleared on all forms of reset. figure 2-5: device clock sources note: the timer1 oscillator must be enabled to switch the system clock source. the timer1 oscillator is enabled by setting the t1oscen bit in the timer1 control register (t1con). if the timer1 oscillator is not enabled, any write to the scs0 bit will be ignored (scs0 bit forced cleared) and the main oscillator will continue to be the sys- tem clock source. PIC18C601/801 t osc 4 x pll t t 1 p t sclk clock source t osc /4 timer 1 oscillator t1oscen enable oscillator t1oso t1osi clock source option for other modules osc1 osc2 sleep main oscillator note: i/o pins have diode protection to v dd and v ss . mux
? 2001 microchip technology inc. advance information ds39541a-page 25 PIC18C601/801 register 2-1: osccon register 2.6.2 oscillator transitions PIC18C601/801 devices contain circuitry to prevent "glitches" when switching between oscillator sources. essentially, the circuitry waits for eight rising edges of the clock source that the processor is switching to. this ensures that the new clock source is stable and that its pulse width will not be less than the shortest pulse width of the two clock sources. a timing diagram indicating the transition from the main oscillator to the timer1 oscillator is shown in figure 2-6. the timer1 oscillator is assumed to be running all the time. after the scs0 bit is set, the processor is frozen at the next occurring q1 cycle. after eight synchroniza- tion cycles are counted from the timer1 oscillator, oper- ation resumes. no additional delays are required after the synchronization cycles. the sequence of events that takes place when switch- ing from the timer1 oscillator to the main oscillator will depend on the mode of the main oscillator. in addition to eight clock cycles of the main oscillator, additional delays may take place. if the main oscillator is configured for an external crys- tal (hs, lp), the transition will take place after an oscil- lator start-up time (t ost ) has occurred. a timing diagram indicating the transition from the timer1 oscil- lator to the main oscillator for hs and lp modes is shown in figure 2-7. u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? ? lock pllen scs1 scs0 bit 7 bit 0 bit 7-4 unimplemented: read as '0' bit 3 lock: phase lock loop lock status bit 1 = phase lock loop output is stable as system clock 0 = phase lock loop output is not stable and cannot be used as system clock bit 2 pllen: phase lock loop enable bit 1 = enable phase lock loop output as system clock 0 = disable phase lock loop bit 1 scs1: system clock switch bit 1 when pllen and lock bit are set: 1 = use pll output 0 = use primary oscillator/clock input pin when pllen bit or lock bit is cleared: bit is forced clear bit 0 scs0: system clock switch bit 0 when t1oscen bit is set: 1 = switch to timer1 oscillator/clock pin 0 = use primary oscillator/clock input pin when t1oscen is cleared: bit is forced clear legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown
PIC18C601/801 ds39541a-page 26 advance information ? 2001 microchip technology inc. figure 2-6: timing diagram for transition from osc1 to timer1 oscillator figure 2-7: timing diagram for transition between timer1 and osc1 (hs, lp) q3 q2 q1 q4 q3 q2 osc1 internal scs0 (osccon<0>) program pc + 2 pc note: delay on internal system clock is eight oscillator cycles for synchronization. q1 t1osi q4 q1 pc + 4 q1 t scs clock counter system q2 q3 q4 q1 t dly t t 1 p t osc 2 1 34 5678 q3 q3 q4 q1 q2 q3 q4 q1 q2 osc1 internal system scs0 (osccon<0>) program counter pc pc + 2 note: t ost = 1024t osc (drawing not to scale). t1osi clock osc2 t ost q1 pc + 4 t t 1 p t osc t scs 12345678
? 2001 microchip technology inc. advance information ds39541a-page 27 PIC18C601/801 if the main oscillator is configured for hs4 (pll) mode with scs1 bit set to ? 1 ? , an oscillator start-up time (t ost ), plus an additional pll time-out (t pll ) will occur. the pll time-out is typically 2 ms and allows the pll to lock to the main oscillator frequency. a timing diagram indicating the transition from the timer1 oscil- lator to the main oscillator for hs4 mode is shown in figure 2-8. if the main oscillator is configured for hs4 (pll) mode, with scs1 bit set to ? 0 ? , only oscillator start-up time (t ost ) will occur. since scs1 bit is set to ? 0 ? , pll out- put is not used, so the system oscillator will come from osc1 directly and additional delay of t pll is not required. a timing diagram indicating the transition from the timer1 oscillator to the main oscillator for hs4 mode is shown in figure 2-9. if the main oscillator is configured in the rc or ec modes, there is no oscillator start-up time-out. opera- tion will resume after eight cycles of the main oscillator have been counted. a timing diagram indicating the transition from the timer1 oscillator to the main oscilla- tor for rc and ec modes is shown in figure 2-10. figure 2-8: timing for transition between timer1 and osc1 (hs4 with scs1 = 1) figure 2-9: timing for transition between timer1 and osc1 (hs4 with scs = 0) q4 q1 q1 q2 q3 q4 q1 q2 osc1 internal system scs 0 (osccon<0>) program counter pc pc + 2 note: t ost = 1024t osc (drawing not to scale). t1osi clock t ost q3 pc + 4 t pll t osc t t 1 p t scs q4 osc2 pll clock input 1234 5678 q4 q1 q1 q2 q3 q4 q1 q2 osc1 internal scs0 (osccon<0>) program pc pc + 2 note: t ost = 1024t osc (drawing not to scale). t1osi clock pll t ost pc + 4 t pll t osc t dly t t 1 p osc2 output counter system clock t scs
PIC18C601/801 ds39541a-page 28 advance information ? 2001 microchip technology inc. figure 2-10: timing for transition between timer1 and osc1 (rc, ec) 2.6.3 scs0, scs1 priority if both scs0 and scs1 are set to ? 1 ? simultaneously, the scs0 bit has priority over the scs1 bit. this means that the low power option will take precedence over the pll option. if both bits are cleared simultaneously, the system clock will come from osc1, after a t ost time- out. if only the scs0 bit is cleared, the system clock will come from the pll output, following t ost and t pll time. table 2-3: scs0, scs1 priority 2.7 effects of sleep mode on the on-chip oscillator when the device executes a sleep instruction, the on-chip clocks and oscillator are turned off and the device is held at the beginning of an instruction cycle (q1 state). with the oscillator off, the osc1 and osc2 signals will stop oscillating. since all the transistor switching currents have been removed, sleep mode achieves the lowest current consumption of the device (only leakage currents). enabling any on-chip feature that will operate during sleep, will increase the cur- rent consumed during sleep. the user can wake from sleep through external reset, watchdog timer reset, or through an interrupt. 2.8 power-up delays power-up delays are controlled by two timers, so that no external reset circuitry is required for most appli- cations. the delays ensure that the device is kept in reset until the device power supply and clock are sta- ble. for additional information on reset operation, see section 3.0 reset. the first timer is the power-up timer (pwrt), which optionally provides a fixed delay of t pwrt (parameter #33) on power-up only. the second timer is the oscil- lator start-up timer (ost), intended to keep the chip in reset until the crystal oscillator is stable. PIC18C601/801 devices provide a configuration bit, pwrten in config2l register, to enable or disable the power-up timer. by default, the power-up timer is enabled. with the pll enabled (hs4 oscillator mode), the time-out sequence following a power-on reset is different from other oscillator modes. the time-out sequence is as fol- lows: the pwrt time-out is invoked after a por time delay has expired, then, the oscillator start-up timer (ost) is invoked. however, this is still not a sufficient amount of time to allow the pll to lock at high frequen- cies. the pwrt timer is used to provide an additional time-out, called t pll (parameter #7), to allow the pll ample time to lock to the incoming clock frequency. table 2-4: osc1 and osc2 pin states in sleep mode q3 q4 q1 q1 q2 q3 q4 q1 q2 q3 osc1 internal system scs0 (osccon<0>) program counter pc pc + 2 note: rc oscillator mode assumed. pc + 4 t1osi clock osc2 q4 t t 1 p t osc t scs 1 23 45 6 78 scs1 scs0 clock source 0 0 ext oscillator osc1 0 1 timer1 oscillator 10hs + pll 1 1 timer1 oscillator osc mode osc1 pin osc2 pin rc floating, external resistor should pull high at logic low ec floating at logic low lp and hs feedback inverter disabled, at quiescent voltage level feedback inverter disabled, at quiescent voltage level note: see table 3-1 in section 3.0 reset, for time-outs due to sleep and mclr reset.
? 2001 microchip technology inc. advance information ds39541a-page 29 PIC18C601/801 3.0 reset PIC18C601/801 devices differentiate between various kinds of reset: a) power-on reset (por) b) mclr reset during normal operation c) mclr reset during sleep d) watchdog timer (wdt) reset during normal operation e) reset instruction f) stack full reset g) stack underflow reset most registers are unaffected by a reset. their status is unknown on por and unchanged by all other resets. the other registers are forced to a ? reset ? state on power-on reset, mclr , wdt reset, mclr reset during sleep, and by the reset instruction. most registers are not affected by a wdt wake-up, since this is viewed as the resumption of normal oper- ation. status bits from the rcon register, ri , to , pd and por, are set or cleared differently in different reset situations, as indicated in table 3-2. these bits are used in software to determine the nature of the reset. see table 3-3 for a full description of the reset states of all registers. a simplified block diagram of the on-chip reset circuit is shown in figure 3-1. PIC18C601/801 has a mclr noise filter in the mclr reset path. the filter will detect and ignore small pulses. a wdt reset does not drive mclr pin low. figure 3-1: simplified block diagram of the on-chip reset circuit s r q external reset mclr v dd osc1 v dd rise detect ost/pwrt on-chip rc osc (1) wdt time-out power-on reset ost 10-bit ripple counter pwrt chip_reset 10-bit ripple counter reset enable ost (2) enable pwrt sleep note 1: this is a separate oscillator from the rc oscillator of the clki pin. 2: see table 3-1 for time-out situations. reset instruction stack pointer stack full/underflow reset wdt module
PIC18C601/801 ds39541a-page 30 advance information ? 2001 microchip technology inc. 3.1 power-on reset (por) a power-on reset pulse is generated on-chip when a v dd rise is detected. to take advantage of the por cir- cuitry, connect the mclr pin directly (or through a resistor) to v dd . this will eliminate external rc compo- nents usually needed to create a power-on reset delay. a minimum rise rate for v dd is specified (param- eter d004). for a slow rise time, see figure 3-2. when the device starts normal operation (exits the reset condition), device operating parameters (volt- age, frequency, temperature, etc.) must be met to ensure operation. if these conditions are not met, the device must be held in reset until the operating con- ditions are met. power-on reset may be used to meet the voltage start-up condition. figure 3-2: external power-on reset circuit (for slow v dd power-up) 3.2 power-up timer (pwrt) the power-up timer provides a fixed nominal time-out (parameter #33), only on power-up from the por. the power-up timer operates on an internal rc oscillator. the chip is kept in reset as long as the pwrt is active. the pwrt time delay allows v dd to rise to an acceptable level. PIC18C601/801 devices are avail- able with pwrt enabled or disabled. the power-up time delay will vary from chip to chip, due to v dd , temperature and process variation. see dc parameter #33 for details. 3.3 oscillator start-up timer (ost) the oscillator start-up timer (ost) provides 1024 oscillator cycle (from osc1 input) delay after the pwrt delay is over (parameter #32). this ensures that the crystal oscillator or resonator has started and stabilized. the ost time-out is invoked only for lp, hs and hs4 modes and only on power-on reset or wake-up from sleep. 3.4 pll lock time-out with the pll enabled, the time-out sequence following a power-on reset is different from other oscillator modes. a portion of the power-up timer is used to pro- vide a fixed time-out that is sufficient for the pll to lock to the main oscillator frequency. this pll lock time-out (t pll ) is typically 1 ms and follows the oscillator start- up time-out (ost). 3.5 time-out sequence on power-up, the time-out sequence is as follows: first, pwrt time-out is invoked after the por time delay has expired; then, ost is activated. the total time-out will vary based on oscillator configuration and the status of the pwrt. for example, in rc mode with the pwrt disabled, there will be no time-out at all. figure 3-3, figure 3-4, figure 3-5, figure 3-6 and figure 3-7 depict time-out sequences on power-up. since the time-outs occur from the por pulse, if mclr is kept low long enough, the time-outs will expire. bringing mclr high will begin execution immediately (figure 3-5). this is useful for testing purposes or to synchronize more than one PIC18C601/801 device operating in parallel. table 3-2 shows the reset conditions for some special function registers, while table 3-3 shows the reset conditions for all registers. note 1: external power-on reset circuit is required only if the v dd power-up slope is too slow. the diode d helps discharge the capacitor quickly when v dd powers down. 2: r < 40 k ? is recommended to make sure that the voltage drop across r does not violate the device ? s electrical specification. 3: r1 = 100 ? to 1 k ? will limit any current flowing into mclr from external capacitor c, in the event of mclr/ v pp pin breakdown due to electrostatic discharge (esd), or electrical overstress (eos). c r1 r d v dd mclr PIC18C601/801
? 2001 microchip technology inc. advance information ds39541a-page 31 PIC18C601/801 table 3-1: time-out in various situations register 3-1: rcon register bits and positions table 3-2: status bits, their significance, and the initialization condition for rcon register oscillator configuration power-up (2) wake-up from sleep or oscillator switch (1) pwrten = 0 pwrten = 1 hs with pll enabled (1) 72 ms + 1024t osc 1024t osc 1024t osc + 1 ms hs, lp 72 ms + 1024t osc 1024t osc 1024t osc ec 72 ms ?? external rc 72 ms ?? note 1: 1 ms is the nominal time required for the 4x pll to lock. maximum time is 2 ms. 2: 72 ms is the nominal power-up timer delay. r/w-0 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 u-0 ipen r ? ri to pd por r bit 7 bit 0 condition program counter rcon register ri to pd por stkful stkunf power-on reset 00000h 0r-1 110r 1 1 1 0 u u mclr reset during normal operation 00000h 0r-u uuur u u u u u u software reset during normal operation 00000h 0r-0 uuur 0 u u u u u stack full reset during normal operation 00000h 0r-u uu1r u u u 1 u 1 stack underflow reset during normal operation 00000h 0r-u uu1r u u u 1 1 u mclr reset during sleep 00000h 0r-u 10ur u 1 0 u u u wdt reset 00000h 0r-u 01ur u 0 1 u u u wdt wake-up pc + 2 ur-u 00ur u 0 0 u u u interrupt wake-up from sleep pc + 2 (1) ur-u 00ur u 0 0 u u u legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', r = reserved, maintain ? 0 ? note 1: when the wake-up is due to an interrupt and the gieh or giel bits are set, the pc is loaded with the interrupt vector ( 000008h or 000018h ).
PIC18C601/801 ds39541a-page 32 advance information ? 2001 microchip technology inc. figure 3-3: time-out sequence on power-up (mclr tied to v dd ) figure 3-4: time-out sequence on power-up (mclr not tied to v dd ): case 1 figure 3-5: time-out sequence on power-up (mclr not tied to v dd ): case 2 t pwrt t ost v dd mclr internal por pwrt time-out ost time-out internal reset t pwrt t ost v dd mclr internal por pwrt time-out ost time-out internal reset v dd mclr internal por pwrt time-out ost time-out internal reset t pwrt t ost
? 2001 microchip technology inc. advance information ds39541a-page 33 PIC18C601/801 figure 3-6: slow rise time (mclr tied to v dd ) figure 3-7: time-out sequence on por w/ pll enabled (mclr tied to v dd ) v dd mclr internal por pwrt time-out ost time-out internal reset 0v 1v 5v t pwrt t ost t deadtime t pwrt t ost v dd mclr iinternal por pwrt time-out ost time-out internal reset pll time-out t pll t ost = 1024 clock cycles. t pll 2 ms max. first three stages of the pwrt timer.
PIC18C601/801 ds39541a-page 34 advance information ? 2001 microchip technology inc. table 3-3: initialization conditions for all registers register applicable devices power-on reset mclr reset wdt reset reset instruction stack over/underflow reset wake-up via wdt or interrupt tosu 601 801 ---0 0000 ---0 0000 ---u uuuu (3) tosh 601 801 0000 0000 0000 0000 uuuu uuuu (3) tosl 601 801 0000 0000 0000 0000 uuuu uuuu (3) stkptr 601 801 00-0 0000 00-0 0000 uu-u uuuu (3) pclatu 601 801 ---0 0000 ---0 0000 ---u uuuu pclath 601 801 0000 0000 0000 0000 uuuu uuuu pcl 601 801 0000 0000 0000 0000 pc + 2 (2) tblptru 601 801 --00 0000 --00 0000 --uu uuuu tblptrh 601 801 0000 0000 0000 0000 uuuu uuuu tblptrl 601 801 0000 0000 0000 0000 uuuu uuuu tablat 601 801 0000 0000 0000 0000 uuuu uuuu prodh 601 801 xxxx xxxx uuuu uuuu uuuu uuuu prodl 601 801 xxxx xxxx uuuu uuuu uuuu uuuu intcon 601 801 0000 000x 0000 000u uuuu uuuu (1) intcon2 601 801 1111 -1-1 1111 -1-1 uuuu -u-u (1) intcon3 601 801 11-0 0-00 11-0 0-00 uu-u u-uu (1) indf0 601 801 (note 5) (note 5) (note 5) postinc0 601 801 (note 5) (note 5) (note 5) postdec0 601 801 (note 5) (note 5) (note 5) preinc0 601 801 (note 5) (note 5) (note 5) plusw0 601 801 (note 5) (note 5) (note 5) fsr0h 601 801 ---- 0000 ---- 0000 ---- uuuu fsr0l 601 801 xxxx xxxx uuuu uuuu uuuu uuuu wreg 601 801 xxxx xxxx uuuu uuuu uuuu uuuu indf1 601 801 (note 5) (note 5) (note 5) postinc1 601 801 (note 5) (note 5) (note 5) postdec1 601 801 (note 5) (note 5) (note 5) preinc1 601 801 (note 5) (note 5) (note 5) plusw1 601 801 (note 5) (note 5) (note 5) fsr1h 601 801 ---- 0000 ---- 0000 ---- uuuu fsr1l 601 801 xxxx xxxx uuuu uuuu uuuu uuuu bsr 601 801 ---- 0000 ---- 0000 ---- uuuu indf2 601 801 (note 5) (note 5) (note 5) legend: u = unchanged, x = unknown, - = unimplemented bit, read as ? 0 ? , q = value depends on condition, r = reserved, maintain ? 0 ? note 1: one or more bits in the intconx or pirx registers will be affected (to cause wake-up). 2: when the wake-up is due to an interrupt and the giel or gieh bit is set, the pc is loaded with the interrupt vector (00008h or 00018h). 3: when the wake-up is due to an interrupt and the giel or gieh bit is set, the tosu, tosh, and tosl are updated with the current value of the pc. the skptr is modified to point to the next location in the hardware stack. 4: see table 3-2 for reset value for specific condition. 5: this is not a physical register. it is an indirect pointer that addresses another register. the contents returned is the value contained in the addressed register.
? 2001 microchip technology inc. advance information ds39541a-page 35 PIC18C601/801 postinc2 601 801 (note 5) (note 5) (note 5) postdec2 601 801 (note 5) (note 5) (note 5) preinc2 601 801 (note 5) (note 5) (note 5) plusw2 601 801 (note 5) (note 5) (note 5) fsr2h 601 801 ---- 0000 ---- 0000 ---- uuuu fsr2l 601 801 xxxx xxxx uuuu uuuu uuuu uuuu status 601 801 ---x xxxx ---u uuuu ---u uuuu tmr0h 601 801 xxxx xxxx uuuu uuuu uuuu uuuu tmr0l 601 801 xxxx xxxx uuuu uuuu uuuu uuuu t0con 601 801 1111 1111 1111 1111 uuuu uuuu osccon 601 801 --00 0-00 --uu u-u0 --uu u-uu lvdcon 601 801 --00 0101 --00 0101 --uu uuuu wdtcon 601 801 ---- 1111 ---- uuuu ---- uuuu rcon (4) 601 801 0r-1 11qr 0r-1 qqur ur-u qqur tmr1h 601 801 xxxx xxxx uuuu uuuu uuuu uuuu tmr1l 601 801 xxxx xxxx uuuu uuuu uuuu uuuu t1con 601 801 0-00 0000 u-uu uuuu u-uu uuuu tmr2 601 801 xxxx xxxx uuuu uuuu uuuu uuuu pr2 601 801 1111 1111 1111 1111 1111 1111 t2con 601 801 -000 0000 -000 0000 -uuu uuuu sspbuf 601 801 xxxx xxxx uuuu uuuu uuuu uuuu sspadd 601 801 0000 0000 0000 0000 uuuu uuuu sspstat 601 801 0000 0000 0000 0000 uuuu uuuu sspcon1 601 801 0000 0000 0000 0000 uuuu uuuu sspcon2 601 801 0000 0000 0000 0000 uuuu uuuu adresh 601 801 xxxx xxxx uuuu uuuu uuuu uuuu adresl 601 801 xxxx xxxx uuuu uuuu uuuu uuuu adcon0 601 801 --00 0000 --00 0000 --uu uuuu adcon1 601 801 -000 0000 -000 0000 -uuu uuuu adcon2 601 801 0--- -000 0--- -000 u--- -uuu ccpr1h 601 801 xxxx xxxx uuuu uuuu uuuu uuuu ccpr1l 601 801 xxxx xxxx uuuu uuuu uuuu uuuu ccp1con 601 801 --00 0000 --00 0000 --uu uuuu table 3-3: initialization conditions for all registers (continued) register applicable devices power-on reset mclr reset wdt reset reset instruction stack over/underflow reset wake-up via wdt or interrupt legend: u = unchanged, x = unknown, - = unimplemented bit, read as ? 0 ? , q = value depends on condition, r = reserved, maintain ? 0 ? note 1: one or more bits in the intconx or pirx registers will be affected (to cause wake-up). 2: when the wake-up is due to an interrupt and the giel or gieh bit is set, the pc is loaded with the interrupt vector (00008h or 00018h). 3: when the wake-up is due to an interrupt and the giel or gieh bit is set, the tosu, tosh, and tosl are updated with the current value of the pc. the skptr is modified to point to the next location in the hardware stack. 4: see table 3-2 for reset value for specific condition. 5: this is not a physical register. it is an indirect pointer that addresses another register. the contents returned is the value contained in the addressed register.
PIC18C601/801 ds39541a-page 36 advance information ? 2001 microchip technology inc. ccpr2h 601 801 xxxx xxxx uuuu uuuu uuuu uuuu ccpr2l 601 801 xxxx xxxx uuuu uuuu uuuu uuuu ccp2con 601 801 --00 0000 --00 0000 --uu uuuu tmr3h 601 801 xxxx xxxx uuuu uuuu uuuu uuuu tmr3l 601 801 xxxx xxxx uuuu uuuu uuuu uuuu t3con 601 801 0000 0000 uuuu uuuu uuuu uuuu spbrg 601 801 xxxx xxxx uuuu uuuu uuuu uuuu rcreg 601 801 xxxx xxxx uuuu uuuu uuuu uuuu txreg 601 801 xxxx xxxx uuuu uuuu uuuu uuuu txsta 601 801 0000 -01x 0000 -01u uuuu -uuu rcsta 601 801 0000 000x 0000 000u uuuu uuuu ipr2 601 801 -1-- 1111 -1-- 1111 -u-- uuuu pir2 601 801 -1-- 0000 -1-- 0000 -u-- uuuu (1) pie2 601 801 -1-- 0000 -1-- 0000 -u-- uuuu ipr1 601 801 1111 1111 1111 1111 uuuu uuuu 601 801 -111 1111 -111 1111 -uuu uuuu pir1 601 801 0000 0000 0000 0000 uuuu uuuu (1) 601 801 -000 0000 -000 0000 -uuu uuuu (1) pie1 601 801 0000 0000 0000 0000 uuuu uuuu 601 801 -000 0000 -000 0000 -uuu uuuu memcon 601 801 0000 --00 0000 --00 uuuu --uu trisj 601 801 1111 1111 1111 1111 uuuu uuuu trish 601 801 1111 1111 1111 1111 uuuu uuuu trisg 601 801 ---1 1111 ---1 1111 ---u uuuu trisf 601 801 1111 1111 1111 1111 uuuu uuuu trise 601 801 1111 1111 1111 1111 uuuu uuuu trisd 601 801 1111 1111 1111 1111 uuuu uuuu trisc 601 801 1111 1111 1111 1111 uuuu uuuu trisb 601 801 1111 1111 1111 1111 uuuu uuuu trisa 601 801 --11 1111 --11 1111 --uu uuuu latg 601 801 ---x xxxx ---u uuuu ---u uuuu latf 601 801 xxxx xxxx uuuu uuuu uuuu uuuu late 601 801 xxxx xxxx uuuu uuuu uuuu uuuu table 3-3: initialization conditions for all registers (continued) register applicable devices power-on reset mclr reset wdt reset reset instruction stack over/underflow reset wake-up via wdt or interrupt legend: u = unchanged, x = unknown, - = unimplemented bit, read as ? 0 ? , q = value depends on condition, r = reserved, maintain ? 0 ? note 1: one or more bits in the intconx or pirx registers will be affected (to cause wake-up). 2: when the wake-up is due to an interrupt and the giel or gieh bit is set, the pc is loaded with the interrupt vector (00008h or 00018h). 3: when the wake-up is due to an interrupt and the giel or gieh bit is set, the tosu, tosh, and tosl are updated with the current value of the pc. the skptr is modified to point to the next location in the hardware stack. 4: see table 3-2 for reset value for specific condition. 5: this is not a physical register. it is an indirect pointer that addresses another register. the contents returned is the value contained in the addressed register.
? 2001 microchip technology inc. advance information ds39541a-page 37 PIC18C601/801 latd 601 801 xxxx xxxx uuuu uuuu uuuu uuuu latc 601 801 xxxx xxxx uuuu uuuu uuuu uuuu latb 601 801 xxxx xxxx uuuu uuuu uuuu uuuu lata 601 801 --xx xxxx --uu uuuu --uu uuuu portj 601 801 xxxx xxxx uuuu uuuu uuuu uuuu porth 601 801 0000 xxxx 0000 uuuu uuuu uuuu portg 601 801 ---x xxxx ---u uuuu ---u uuuu portf 601 801 xxxx x000 uuuu u000 uuuu uuuu porte 601 801 xxxx xxxx uuuu uuuu uuuu uuuu portd 601 801 xxxx xxxx uuuu uuuu uuuu uuuu portc 601 801 xxxx xxxx uuuu uuuu uuuu uuuu portb 601 801 xxxx xxxx uuuu uuuu uuuu uuuu porta 601 801 --0x 0000 --0u 0000 --uu uuuu csel2 601 801 1111 1111 uuuu uuuu uuuu uuuu cselio 601 801 1111 1111 uuuu uuuu uuuu uuuu table 3-3: initialization conditions for all registers (continued) register applicable devices power-on reset mclr reset wdt reset reset instruction stack over/underflow reset wake-up via wdt or interrupt legend: u = unchanged, x = unknown, - = unimplemented bit, read as ? 0 ? , q = value depends on condition, r = reserved, maintain ? 0 ? note 1: one or more bits in the intconx or pirx registers will be affected (to cause wake-up). 2: when the wake-up is due to an interrupt and the giel or gieh bit is set, the pc is loaded with the interrupt vector (00008h or 00018h). 3: when the wake-up is due to an interrupt and the giel or gieh bit is set, the tosu, tosh, and tosl are updated with the current value of the pc. the skptr is modified to point to the next location in the hardware stack. 4: see table 3-2 for reset value for specific condition. 5: this is not a physical register. it is an indirect pointer that addresses another register. the contents returned is the value contained in the addressed register.
PIC18C601/801 ds39541a-page 38 advance information ? 2001 microchip technology inc. notes:
? 2001 microchip technology inc. advance information ds39541a-page 39 PIC18C601/801 4.0 memory organization there are two memory blocks in PIC18C601/801 devices. these memory blocks are: program memory data memory each block has its own bus so that concurrent access can occur. 4.1 program memory organization PIC18C601/801 devices have a 21-bit program counter that is capable of addressing up to 2 mbyte of external program memory space. the PIC18C601 has an external program memory address space of 256 kbytes. any program fetch or tblrd from a program location greater than 256k will return all nop s. the pic18c801 has an external program memory address space of 2mbytes. refer to section 5.0 ( ? external memory interface ? ) for additional details. the reset vector address is mapped to 000000h and the interrupt vector addresses are at 000008h and 000018h. PIC18C601/801 devices have a 31-level stack to store the program counter values during subroutine calls and interrupts. figure 4-1 shows the program memory map and stack for PIC18C601. figure 4-2 shows the program memory map and stack for the pic18c801. 4.1.1 ? boot ram ? program memory PIC18C601/801 devices have a provision for configur- ing the last 512 bytes of general purpose user ram as program memory, called ? boot ram ? . this is achieved by configuring the pgrm bit in the memcon register to ? 1 ? . (refer to section 5.0, ? external memory inter- face ? for more information.) when the pgrm bit is ? 1 ? , the ram located in data memory locations 400h through 5ffh (bank 4 through 5) is mapped to program memory locations 1ffe00h to 1fffffh. when configured as program memory, the boot ram is to be used as a temporary ? boot loader ? for program- ming purposes. it can only be used for program execu- tion. a read from locations 400h to 5ffh in data memory returns all ? 0 ? s. any attempt to write this ram as data memory when pgrm = 1, does not modify any of these locations. tblwt instructions to these loca- tions will cause writes to occur on the external memory bus. the boot ram program memory cannot be modi- fied using tblwt instruction. tblrd instructions from boot ram will read memory located on the external memory bus, not from the on-board ram. constants that are stored in boot ram are retrieved using the retlw instruction. the default reset state (power-up) for the pgrm bit is ? 0 ? , which configures 1.5k of data ram and all pro- gram memory as external. the pgrm bit can be set and cleared in the software. when execution takes place from ? boot ram ? , the external system bus and all of its control signals will be deactivated. if execution takes place from outside of ? boot ram ? , the external system bus and all of its con- trol signals are activated again. figure 4-3 and figure 4-4 show the program memory map and stack for PIC18C601 and pic18c801, when the pgrm bit is set.
PIC18C601/801 ds39541a-page 40 advance information ? 2001 microchip technology inc. figure 4-1: program memory map and stack for PIC18C601 (pgrm = 0) figure 4-2: program memory map and stack for pic18c801 (pgrm = 0) pc<20:0> stack level 1 ? stack level 31 reset vector low priority interrupt vector ? ? 21 0000h 0018h 40000h 3ffffh external program memory high priority interrupt vector 0008h user memory space read ? 0 ? 1fffffh pc<20:0> stack level 1 ? stack level 31 reset vector low priority interrupt vector ? ? 21 0000h 0018h external program memory high priority interrupt vector 0008h user memory space 1fffffh
? 2001 microchip technology inc. advance information ds39541a-page 41 PIC18C601/801 figure 4-3: program memory map and stack for PIC18C601 (pgrm = 1) pc<20:0> stack level 1 ? stack level 31 reset vector low priority interrupt vector ? ? 21 0000h 0018h 040000h 03ffffh external program memory high priority interrupt vector 0008h user memory space read ? 0 ? 1fffffh 1ffdffh 1ffe00h 1fffffh 1ffe00h on-chip boot ram external memory internal memory
PIC18C601/801 ds39541a-page 42 advance information ? 2001 microchip technology inc. figure 4-4: program memory map and stack for pic18c801 (pgrm = 1) pc<20:0> stack level 1 ? stack level 31 reset vector low priority interrupt vector ? ? 21 0000h 0018h external program memory high priority interrupt vector 0008h user memory space 1fffffh 1ffdffh 1ffe00h external table memory 1fffffh 1ffe00h on-chip boot ram external memory internal memory
? 2001 microchip technology inc. advance information ds39541a-page 43 PIC18C601/801 4.1.2 boot loader when configured as program memory, boot ram can be used as a temporary ? boot loader ? for programming purposes. if an external memory device is used as pro- gram memory, any updates performed by the user pro- gram will have to be performed in the ? boot ram ? , because the user program cannot program and fetch from external memory, simultaneously. a typical boot loader execution and external memory programming sequence would be as follows: the boot loader program is transferred from the external program memory to the last 2 banks of data ram by tblrd and movwf instructions. once the ? boot loader ? program is loaded into internal memory and verified, open combination lock and set pgrm bit to configure the data ram into program ram. jump to beginning of boot code in boot ram. program execution begins in boot ram to begin programming the external memory. system bus changes to an inactive state. boot loader program performs the necessary external tblwt and tblwrd instructions to perform programming functions. when the boot loader program is finished pro- gramming external memory, jump to known valid external program memory location and clear pgrm bit in memcon register to set boot ram as data memory, or reset the part. 4.2 return address stack the return address stack allows any combination of up to 31 program calls and interrupts to occur. the pc (pro- gram counter) is pushed onto the stack when a push, call or rcall instruction is executed, or an interrupt is acknowledged. the pc value is pulled off the stack on a return, retlw or a retfie instruction. pclatu and pclath are not affected by any of the return instructions. the stack operates as a 31-word by 21-bit stack memory and a five-bit stack pointer, with the stack pointer initial- ized to 00000b after all resets. there is no ram asso- ciated with stack pointer 00000b . this is only a reset value. during a call type instruction, causing a push onto the stack, the stack pointer is first incremented and the ram location pointed to by the stack pointer is written with the contents of the pc. during a return type instruction, causing a pop from the stack, the contents of the ram location indicated by the stkptr is transferred to the pc and then the stack pointer is decremented. the stack space is not part of either program or data space. the stack pointer is readable and writable, and the data on the top of the stack is readable and writable through sfr registers. status bits stkovf and stkunf in stkptr register, indicate whether stack over/underflow has occurred or not. 4.2.1 top-of-stack access the top of the stack is readable and writable. three register locations, tosu, tosh and tosl, allow access to the contents of the stack location indicated by the stkptr register. this allows users to implement a software stack, if necessary. after a call, rcall or interrupt, the software can read the pushed value by reading the tosu, tosh and tosl registers. these values can be placed on a user defined software stack. at return time, the software can replace the tosu, tosh and tosl and do a return. the user should disable the global interrupt enable bits during this time to prevent inadvertent stack operations. 4.2.2 return stack pointer (stkptr) the stkptr register contains the stack pointer value, the stkful (stack full) status bit, and the stkunf (stack underflow) status bits. register 4-1 shows the stkptr register. the value of the stack pointer can be 0 through 31. the stack pointer increments when val- ues are pushed onto the stack and decrements when values are popped off the stack. at reset, the stack pointer value will be 0. the user may read and write the stack pointer value. this feature can be used by a real time operating system for return stack maintenance. after the pc is pushed onto the stack 31 times (without popping any values off the stack), the stkful bit is set. the stkful bit can only be cleared in software or by a por. any subsequent push operation that causes stack overflow will be ignored. the action that takes place when the stack becomes full, depends on the state of stvren (stack overflow reset enable) configuration bit in config4l regis- ter. refer to section 4.2.4 for more information. if stvren is set (default), stack over/underflow will set the stkful bit, and reset the device. the stkful bit will remain set and the stack pointer will be set to 0. if stvren is cleared, the stkful bit will be set on the 31st push and the stack pointer will increment to 31. all subsequent push attempts will be ignored and stkptr remains at 31. when the stack has been popped enough times to unload the stack, the next pop will return a value of zero to the pc and sets the stkunf bit, while the stack pointer remains at 0. the stkunf bit will remain set until cleared in software, or a por occurs. note: returning a value of zero to the pc on an underflow has the effect of vectoring the program to the reset vector, where the stack conditions can be verified and appro- priate actions can be taken.
PIC18C601/801 ds39541a-page 44 advance information ? 2001 microchip technology inc. register 4-1: stkptr - stack pointer register figure 4-5: return address stack and associated registers r/c-0 r/c-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 stkful stkunf ? sp4 sp3 sp2 sp1 sp0 bit 7 bit 0 bit 7 stkful : stack full flag bit 1 = stack became full or overflowed 0 = stack has not become full or overflowed bit 6 stkunf : stack underflow flag bit 1 = stack underflow occurred 0 = stack underflow did not occur bit 5 unimplemented : read as '0' bit 4-0 sp4:sp0 : stack pointer location bits note: bit 7 and bit 6 can only be cleared in user software, or by a por. legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared c = clearable bit 00011 001a34h 11111 11110 11101 00010 00001 00000 (1) 00010 return address stack top-of-stack 000d58h tosl tosh tosu 34h 1ah 00h stkptr<4:0> 000000h note 1: no ram is associated with this address; always maintained ? 0 ? s.
? 2001 microchip technology inc. advance information ds39541a-page 45 PIC18C601/801 4.2.3 push and pop instructions since the top-of-stack (tos) is readable and writable, the ability to push values onto the stack and pop values off the stack, without disturbing normal program execu- tion, is a desirable option. to push the current pc value onto the stack, a push instruction can be executed. this will increment the stack pointer and load the cur- rent pc value onto the stack. tosu, tosh and tosl can then be modified to place a return address on the stack. the pop instruction discards the current tos by decre- menting the stack pointer. the previous value pushed onto the stack then becomes the tos value. 4.2.4 stack full/underflow resets these resets are enabled/disabled by programming the stvren configuration bit in config4l register. when the stvren bit is disabled, a full or underflow condition will set the appropriate stkful or stkunf bit, but not cause a reset. when the stvren bit is enabled, a full or underflow will set the appropriate stkful or stkunf bit and then cause a reset. the stkful or stkunf bits are only cleared by the user software or a por. 4.3 fast register stack a ? fast return ? option is available for interrupts and calls. a fast register stack is provided for the status, wreg and bsr registers, and is only one layer in depth. the stack is not readable or writable and is loaded with the current value of the corresponding register when the processor vectors for an interrupt. the values in the fast register stack are then loaded back into the working reg- isters, if the fast return instruction is used to return from the interrupt. a low or high priority interrupt source will push values into the stack registers. if both low and high priority interrupts are enabled, the stack registers cannot be used reliably for low priority interrupts. if a high priority interrupt occurs while servicing a low priority interrupt, the stack register values stored by the low priority interrupt will be overwritten. if high priority interrupts are not disabled during low pri- ority interrupts, users must save the key registers in software during a low priority interrupt. if no interrupts are used, the fast register stack can be used to restore the status, wreg and bsr registers at the end of a subroutine call. to use the fast register stack for a subroutine call, a fast call instruction must be executed. example 4-1 shows a source code example that uses the fast register stack. example 4-1: fast register stack code example call sub1, fast ;status, wreg, bsr ;saved in fast register ;stack ? ? sub1 ? ? ? return fast ;restore values saved ;in fast register stack
PIC18C601/801 ds39541a-page 46 advance information ? 2001 microchip technology inc. 4.4 pcl, pclath and pclatu the program counter (pc) specifies the address of the instruction to fetch for execution. the pc is 21-bits wide. the low byte is called the pcl register. this reg- ister is readable and writable. the high byte is called the pch register. this register contains the pc<15:8> bits and is not directly readable or writable. updates to the pch register may be performed through the pclath register. the upper byte is called pcu. this register contains the pc<20:16> bits and is not directly readable or writable. updates to the pcu register may be performed through the pclatu register. the pc addresses bytes in the program memory. to prevent the pc from becoming misaligned with word instructions, the lsb of the pcl is fixed to a value of ? 0 ? . the pc increments by 2 to address sequential instruc- tions in the program memory. the call, rcall, goto and program branch instructions write to the program counter directly. for these instructions, the contents of pclath and pclatu are not transferred to the program counter. the contents of pclath and pclatu will be trans- ferred to the program counter by an operation that writes pcl. similarly, the upper two bytes of the pro- gram counter will be transferred to pclath and pclatu by an operation that reads pcl. this is useful for computed offsets to the pc (see section 4.8.1). 4.5 clocking scheme/instruction cycle the clock input (from osc1 or pll output) is internally divided by four to generate four non-overlapping quadrature clocks, namely q1, q2, q3 and q4. inter- nally, the program counter (pc) is incremented every q1, the instruction is fetched from the program memory and latched into the instruction register in q4. the instruction is decoded and executed during the follow- ing q1 through q4. the clocks and instruction execu- tion flow are shown in figure 4-6. figure 4-6: clock/instruction cycle q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 osc1 q1 q2 q3 q4 pc osc2/clkout (rc mode) pc pc+2 pc+4 fetch inst (pc) execute inst (pc-2) fetch inst (pc+2) execute inst (pc) fetch inst (pc+4) execute inst (pc+2) internal phase clock
? 2001 microchip technology inc. advance information ds39541a-page 47 PIC18C601/801 4.6 instruction flow/pipelining an ? instruction cycle ? consists of four q cycles (q1, q2, q3 and q4). the instruction fetch and execute are pipelined, such that fetch takes one instruction cycle, while decode and execute takes another instruction cycle. however, due to the pipelining, each instruction effectively executes in one cycle. if an instruction causes the program counter to change (e.g., goto ), two cycles are required to complete the instruction (example 4-2). a fetch cycle begins with the program counter (pc) incrementing in q1. in the execution cycle, the fetched instruction is latched into the ? instruction register ? (ir) in cycle q1. this instruction is then decoded and executed during the q2, q3, and q4 cycles. data memory is read during q2 (operand read) and written during q4 (destination write). 4.7 instructions in program memory the program memory is addressed in bytes. instruc- tions are stored as two bytes or four bytes in program memory. the least significant byte of an instruction word is always stored in a program memory location with an even address (lsb = ? 0 ? ). figure 4-1 shows an example of how instruction words are stored in the pro- gram memory. to maintain alignment with instruction boundaries, the pc increments in steps of 2 and the lsb will always read ? 0 ? (see section 4.4). the call and goto instructions have an absolute pro- gram memory address embedded into the instruction. since instructions are always stored on word bound- aries, the data contained in the instruction is a word address. the word address is written to pc<20:1>, which accesses the desired byte address in program memory. instruction #2 in figure 4-1 shows how the instruction ? goto 0x06 ? is encoded in the program memory. program branch instructions that encode a relative address offset operate in the same manner. the offset value stored in a branch instruction repre- sents the number of single word instructions by which the pc will be offset. section 20.0 provides further details of the instruction set. example 4-2: instruction pipeline flow table 4-1: instructions in program memory instruction opcode memory address ? ?? 000007h movlw 055h 0e55h 55h 000008h 0eh 000009h goto 000006h ef03h, f000h 03h 00000ah efh 00000bh 00h 00000ch f0h 00000dh movff 123h, 456h c123h, f456h 23h 00000eh c1h 00000fh 56h 000010h f4h 000011h ? ?? 000012h all instructions are single cycle, except for any program branches. these take two cycles, since the fetch instruction is ? flushed ? from the pipeline, while the new instruction is being fetched and then executed. t cy 0t cy 1t cy 2t cy 3t cy 4t cy 5 1. movlw 55h fetch 1 execute 1 2. movwf portb fetch 2 execute 2 3. bra sub_1 fetch 3 execute 3 4. bsf porta, bit3 (forced nop) fetch 4 flush 5. instruction @ address sub_1 fetch sub_1 execute sub_1
PIC18C601/801 ds39541a-page 48 advance information ? 2001 microchip technology inc. 4.7.1 two-word instructions PIC18C601/801 devices have four two-word instruc- tions: movff, call, goto and lfsr . the second word of these instructions has the four msb ? s set to 1 ? s and is a special kind of nop instruction. the lower 12 bits of the second word contain data to be used by the instruction. if the first word of the instruction is exe- cuted, the data in the second word is accessed. if the second word of the instruction is executed by itself (first word was skipped), it will execute as a nop . this action is necessary when the two-word instruction is preceded by a conditional instruction that changes the pc and skips one instruction. a program example that demon- strates this concept is shown in example 4-3. refer to section 19.0 for further details of the instruction set. 4.8 lookup tables lookup tables are implemented two ways: computed goto table reads 4.8.1 computed goto a computed goto is accomplished by adding an offset to the program counter ( addwf pcl ). a lookup table can be formed with an addwf pcl instruction and a group of retlw 0xnn instructions. wreg is loaded with an offset into the table, before exe- cuting a call to that table. the first instruction of the called routine is the addwf pcl instruction. the next instruc- tion executed will be one of the retlw 0xnn instruc- tions that returns the value 0xnn to the calling function. the offset value (value in wreg) specifies the number of bytes that the program counter should advance. in this method, only one data byte may be stored in each instruction location and room on the return address stack is required. 4.8.2 table reads/table writes a better method of storing data in program memory allows 2 bytes of data to be stored in each instruction location. lookup table data may be stored as 2 bytes per pro- gram word by using table reads and writes. the table pointer (tblptr) specifies the byte address and the table latch (tablat) contains the data that is read from, or written to, program memory. data is trans- ferred to/from program memory one byte at a time. a description of the table read/table write operation is shown in section 6.0. example 4-3: two-word instructions warning: the lsb of the pcl is fixed to a value of ? 0 ? . hence, computed goto to an odd address is not possible. note: if execution is taking place from boot ram program memory, retlw instructions must be used to read lookup values from the boot ram itself. case 1: object code source code 0110 0110 0000 0000 tstfsz reg1 ; is ram location 0? 1100 0001 0010 0011 movff reg1, reg2 ; no, execute 2-word instruction 1111 0100 0101 0110 ; 2nd operand holds address of reg2 0010 0100 0000 0000 addwf reg3 ; continue code case 2: object code source code 0110 0110 0000 0000 tstfsz reg1 ; is ram location 0? 1100 0001 0010 0011 movff reg1, reg2 ; yes 1111 0100 0101 0110 ; 2nd operand executed as nop 0010 0100 0000 0000 addwf reg3 ; continue code
? 2001 microchip technology inc. advance information ds39541a-page 49 PIC18C601/801 4.9 data memory organization the data memory is implemented as static ram. each register in the data memory has a 12-bit address, allow- ing up to 4096 bytes of data memory. figure 4-8 shows the data memory organization for PIC18C601/801 devices. the data memory map is divided into banks that con- tain 256 bytes each. the lower four bits of the bank select register (bsr<3:0>) select which bank will be accessed. the upper 4 bits for the bsr are not imple- mented. the data memory contains special function registers (sfr) and general purpose registers (gpr). the sfr ? s are used for control and status of the controller and peripheral functions, while gpr ? s are used for data storage and scratch pad operations in the user ? s appli- cation. the sfr ? s start at the last location of bank 15 (0fffh) and grow downwards. gpr ? s start at the first location of bank 0 and grow upwards. any read of an unimplemented location will read as ? 0 ? s. gpr banks 4 and 5 serve as a program memory called ? boot ram ? , when pgrm bit in memcon is set. when pgrm bit is set, any read from ? boot ram ? returns ? 0 ? s, while any write to it is ignored. the entire data memory may be accessed directly or indirectly. direct addressing may require the use of the bsr register. indirect addressing requires the use of a file select register (fsr). each fsr holds a 12-bit address value that can be used to access any location in the data memory map without banking. the instruction set and architecture allow operations across all banks. this may be accomplished by indirect addressing, or by the use of the movff instruction. the movff instruction is a two-word/two-cycle instruction that moves a value from one register to another. to ensure that commonly used registers (sfrs and select gprs) can be accessed in a single cycle, regardless of the current bsr values, an access bank is implemented. a segment of bank 0 and a segment of bank 15 comprise the access bank. section 4.10 pro- vides a detailed description of the access bank. 4.9.1 general purpose register file the register file can be accessed either directly or indi- rectly. indirect addressing operates through the file select registers (fsr). the operation of indirect addressing is shown in section 4.12. PIC18C601/801 devices have banked memory in the gpr area. gprs are not initialized by a power-on reset and are unchanged on all other resets. data ram is available for use as gpr registers by all instructions. bank 15 (0f80h to 0fffh) contains sfr ? s. all other banks of data memory contain gpr registers starting with bank 0. 4.9.2 special function registers the special function registers (sfrs) are registers used by the cpu and peripheral modules for control- ling the desired operation of the device. these regis- ters are implemented as static ram. a list of these registers is given in table 4-2. the sfr ? s can be classified into two sets: those asso- ciated with the ? core ? function and those related to the peripheral functions. those registers related to the ? core ? are described in this section, while those related to the operation of the peripheral features are described in the section of that peripheral feature. the sfrs are typically distributed among the peripher- als whose functions they control. the unused sfr locations are unimplemented and read as '0's. see table 4-2 for addresses for the sfrs. 4.9.3 secured access registers PIC18C601/801 devices contain software program- ming options for safety critical peripherals. because these safety critical peripherals can be programmed in software, registers used to control these peripherals are given limited access by the user code. this way, errant code will not accidentally change settings in peripherals that could cause catastrophic results. the registers that are considered safety critical are the watchdog timer register (wdtcon), the external memory control register (memcon), the oscillator control register (osccon) and the chip select regis- ters (cssel2 and cselio). two bits called combination lock (cmlk) bits, located in the lower two bits of the pspcon register, must be set in sequence by user code to gain access to secured access registers.
PIC18C601/801 ds39541a-page 50 advance information ? 2001 microchip technology inc. register 4-2: pspcon register the combination lock bits must be set sequentially, meaning that as soon as combination lock bit cmlk1 is set, the second combination lock bit cmlk0 must be set on the following instruction cycle. if user waits more than one machine cycle to set the second bit after set- ting the first, both bits will automatically be cleared in hardware and the lock will remain closed. to satisfy this condition, all interrupts must be disabled before attempt- ing to unlock the combination lock. once secured reg- isters are modified, interrupts may be re-enabled. each instruction must only modify one combination lock bit at a time. this means, user code must use the bsf instruction to set cmlk bits in the pspcon register. when the combination lock is opened, the user will have three instruction cycles to modify the safety criti- cal register of choice. after three instruction cycles have expired, the cmlk bits are cleared, the lock will close and the user will have to set the cmlk bits again, in order to open the lock. since there are only three instruction cycles allowed after the combination lock is opened, if a subroutine is used to unlock combination lock bits, user code must preload wreg with the desired value, call unlock subroutine, and write to the desired safety critical register itself. example 4-4: combination unlock subroutine example code u-0 u-0 u-0 u-0 u-0 u-0 w-0 w-0 ? ? ? ? ? ? cmlk1 cmlk0 bit 7 bit 0 bit 7-2 unimplemented : read as '0' bit 1-0 cmlk<1:0> : combination lock bits legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown note: the combination lock bits are write-only bits. these bits will always return ? 0 ? when read. note: successive attempts to unlock the combi- nation lock must be separated by at least three instruction cycles. movlw 5ah ; preload wreg with data to be stored in a safety critical register bcf intcon, gie ; disable all interrupts call unlock ; now unlock it ; write must take place in next instruction cycle movwf osccon ; lock is closed bsf intcon, gie ; re-enable interrupts ? ? unlock bsf pspcon, cmlk1 bsf pspcon, cmlk0 return ? ?
? 2001 microchip technology inc. advance information ds39541a-page 51 PIC18C601/801 example 4-5: combination unlock macro example code figure 4-7: the data memory map for pic18c801/601 (pgrm = 0) unlock_n_modify @reg macro bcf intcon, gie ; disable interrupts bsf pspcon, cmlk1 bsf pspcon, cmlk0 movwf @reg ; modify given register bsf intcon, gie ; enable interrupts endm ? ? movlw 5ah ; preload wreg for osccon register unlock_n_modify osccon ; modify osccon bank 0 bank 1 bank 14 bank 15 data memory map bsr<3:0> = 0000b = 0001b = 1111b 080h 07fh f80h fffh when a = 0, the bsr is ignored and this access ram bank is used. the first 128 bytes are general purpose ram (from bank 0). the next 128 bytes are special function registers (from bank 15). when a = 1, the bsr is used to specify the ram location that the instruction uses. bank 3 bank 2 f7fh f00h effh 3ffh 300h 2ffh 200h 1ffh 100h 0ffh 000h = 0011b = 0010b access gpr ? s ffh 00h ffh 00h ffh 00h ffh 00h ffh 00h gpr gpr gpr gpr access sfr ? s unused bank 6 to unused read ? 00h ? = 1110b = 0110b 5ffh 500h 4ffh 400h ffh 00h ffh 00h 00h 7fh ffh access ram bank access bank high access bank low (gpr ? s) (sfr ? s) 80h bank 4 = 0100b bank 5 = 0101b gpr gpr
PIC18C601/801 ds39541a-page 52 advance information ? 2001 microchip technology inc. figure 4-8: data memory map for PIC18C601/801 (pgrm = 1) bank 0 bank 1 bank 14 bank 15 data memory map bsr<3:0> = 0000b = 0001b = 1111b 080h 07fh f80h fffh 00h 7fh 80h ffh access ram bank when a = 0, the bsr is ignored and this access ram bank is used. the first 128 bytes are general purpose ram (from bank 0). the next 128 bytes are special function registers (from bank 15). bank 3 bank 2 f7fh f00h effh 3ffh 300h 2ffh 200h 1ffh 100h 0ffh 000h = 0011b = 0010b access gpr ? s ffh 00h ffh 00h ffh 00h ffh 00h ffh 00h gpr gpr gpr gpr access bank high access bank low bank 4 to unused read ? 00h ? = 1110b = 0100b (gpr ? s) (sfr ? s) when a = 1, the bsr is used to specify the ram location that the instruction uses. access sfr ? s unused
? 2001 microchip technology inc. advance information ds39541a-page 53 PIC18C601/801 figure 4-9: special function register map fffh tosu fdfh indf2 fbfh ccpr1h f9fh ipr1 ffeh tosh fdeh postinc2 fbeh ccpr1l f9eh pir1 ffdh tosl fddh postdec2 fbdh ccp1con f9dh pie1 ffch stkptr fdch preinc2 fbch ccpr2h f9ch memcon ffbh pclatu fdbh plusw2 fbbh ccpr2l f9bh ? ffah pclath fdah fsr2h fbah ccp2con f9ah trisj ff9h pcl fd9h fsr2l fb9h reserved f99h trish ff8h tblptru fd8h status fb8h reserved f98h trisg ff7h tblptrh fd7h tmr0h fb7h reserved f97h trisf ff6h tblptrl fd6h tmr0l fb6h ? f96h trise ff5h tablat fd5h t0con fb5h ? f95h trisd ff4h prodh fd4h reserved fb4h ? f94h trisc ff3h prodl fd3h osccon fb3h tmr3h f93h trisb ff2h intcon fd2h lvdcon fb2h tmr3l f92h trisa ff1h intcon2 fd1h wdtcon fb1h t3con f91h latj ff0h intcon3 fd0h rcon fb0h pspcon f90h lath fefh indf0 fcfh tmr1h fafh spbrg f8fh latg feeh postinc0 fceh tmr1l faeh rcreg f8eh latf fedh postdec0 fcdh t1con fadh txreg f8dh late fech preinc0 fcch tmr2 fach txsta f8ch latd febh plusw0 fcbh pr2 fabh rcsta f8bh latc feah fsr0h fcah t2con faah ? f8ah latb fe9h fsr0l fc9h sspbuf fa9h ? f89h lata fe8h wreg fc8h sspadd fa8h ? f88h portj fe7h indf1 fc7h sspstat fa7h csel2 f87h porth fe6h postinc1 fc6h sspcon1 fa6h cselio f86h portg fe5h postdec1 fc5h sspcon2 fa5h ? f85h portf fe4h preinc1 fc4h adresh fa4h ? f84h porte fe3h plusw1 fc3h adresl fa3h ? f83h portd fe2h fsr1h fc2h adcon0 fa2h ipr2 f82h portc fe1h fsr1l fc1h adcon1 fa1h pir2 f81h portb fe0h bsr fc0h adcon2 fa0h pie2 f80h porta
PIC18C601/801 ds39541a-page 54 advance information ? 2001 microchip technology inc. table 4-2: register file summary - PIC18C601/801 file name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por value on all other resets (1) fffh tosu ? ? ? top-of-stack upper byte (tos<20:16>) ---0 0000 ---0 0000 ffeh tosh top-of-stack high byte (tos<15:8>) 0000 0000 0000 0000 ffdh tosl top-of-stack low byte (tos<7:0>) 0000 0000 0000 0000 ffch stkptr stkovf stkunf ? return stack pointer 00-0 0000 00-0 0000 ffbh pclatu ? ? ? holding register for pc<20:16> ---0 0000 ---0 0000 ffah pclath holding register for pc<15:8> 0000 0000 0000 0000 ff9h pcl pc low byte (pc<7:0>) 0000 0000 0000 0000 ff8h tblptru ? ? r program memory table pointer upper byte (tblptr<20:16>) --r0 0000 --r0 0000 ff7h tblptrh program memory table pointer high byte (tblptr<15:8>) 0000 0000 0000 0000 ff6h tblptrl program memory table pointer low byte (tblptr<7:0>) 0000 0000 0000 0000 ff5h tablat program memory table latch 0000 0000 0000 0000 ff4h prodh product register high byte xxxx xxxx uuuu uuuu ff3h prodl product register low byte xxxx xxxx uuuu uuuu ff2h intcon gie/gieh peie/giel tmr0ie int0e rbie tmr0if int0f rbif 0000 000x 0000 000u ff1h intcon2 rbpu intedg0 intedg1 intedg2 ? t0ip ? rbip 1111 -1-1 1111 -1-1 ff0h intcon3 int2p int1p ? int2e int1e ? int2f int1f 11-0 0-00 11-0 0-00 fefh indf0 uses contents of fsr0 to address data memory - value of fsr0 not changed (not a physical register) n/a n/a feeh postinc0 uses contents of fsr0 to address data memory - value of fsr0 post-incremented (not a physical register) n/a n/a fedh postdec0 uses contents of fsr0 to address data memory - value of fsr0 post-decremented (not a physical register) n/a n/a fech preinc0 uses contents of fsr0 to address data memory - value of fsr0 pre-incremented (not a physical register) n/a n/a febh plusw0 uses contents of fsr0 to address data memory -value of fsr0 offset by wreg (not a physical register) n/a n/a feah fsr0h ? ? ? ? indirect data memory address pointer 0 high ---- xxxx ---- uuuu fe9h fsr0l indirect data memory address pointer 0 low byte xxxx xxxx uuuu uuuu fe8h wreg working register xxxx xxxx uuuu uuuu fe7h indf1 uses contents of fsr1 to address data memory - value of fsr1 not changed (not a physical register) n/a n/a fe6h postinc1 uses contents of fsr1 to address data memory - value of fsr1 post-incremented (not a physical register) n/a n/a fe5h postdec1 uses contents of fsr1 to address data memory - value of fsr1 post-decremented (not a physical register) n/a n/a fe4h preinc1 uses contents of fsr1 to address data memory - value of fsr1 pre-incremented (not a physical register) n/a n/a fe3h plusw1 uses contents of fsr1 to address data memory - value of fsr1 offset by wreg (not a physical register) n/a n/a fe2h fsr1h ? ? ? ? indirect data memory address pointer 1 high ---- xxxx ---- uuuu fe1h fsr1l indirect data memory address pointer 1 low byte xxxx xxxx uuuu uuuu fe0h bsr ? ? ? ? bank select register ---- 0000 ---- 0000 fdfh indf2 uses contents of fsr2 to address data memory - value of fsr2 not changed (not a physical register) n/a n/a fdeh postinc2 uses contents of fsr2 to address data memory - value of fsr2 post-incremented (not a physical register) n/a n/a fddh postdec2 uses contents of fsr2 to address data memory - value of fsr2 post-decremented (not a physical register) n/a n/a fdch preinc2 uses contents of fsr2 to address data memory - value of fsr2 pre-incremented (not a physical register) n/a n/a fdbh plusw2 uses contents of fsr2 to address data memory -value of fsr2 offset by wreg (not a physical register) n/a n/a fdah fsr2h ? ? ? ? indirect data memory address pointer 2 high ---- xxxx ---- uuuu fd9h fsr2l indirect data memory address pointer 2 low byte xxxx xxxx uuuu uuuu fd8h status ? ? ? nov z dcc ---x xxxx ---u uuuu legend x = unknown, u = unchanged, - = unimplemented, q = value depends on condition, r = reserved note 1: other (non-power-up) resets include external reset through mclr and watchdog timer reset. 2: these registers can only be modified when the combination lock is open. 3: these registers are available on pic18c801 only.
? 2001 microchip technology inc. advance information ds39541a-page 55 PIC18C601/801 fd7h tmr0h timer0 register high byte 0000 0000 0000 0000 fd6h tmr0l timer0 register low byte xxxx xxxx uuuu uuuu fd5h t0con tmr0on 16bit t0cs t0se t0ps3 t0ps2 t0ps1 t0ps0 1111 1111 1111 1111 fd4h reserved rrrr rrrr rrrr rrrr fd3h osccon (2) ? ? ? ? lock pllen scs1 scs0 ---- 0000 ---- uuu0 fd2h lvdcon (2) ? ? irvst lvden lvv3 lvv2 lvv1 lvv0 --00 0101 --00 0101 fd1h wdtcon (2) ? ? ? ? wdps2 wdps1 wdps0 swdten ---- 0000 ---- xxxx fd0h rcon ipen r ? ri to pd por r 00-1 11qq 00-q qquu fcfh tmr1h timer1 register high byte xxxx xxxx uuuu uuuu fceh tmr1l timer1 register low byte xxxx xxxx uuuu uuuu fcdh t1con rd16 ? t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on 0-00 0000 u-uu uuuu fcch tmr2 timer2 register 0000 0000 0000 0000 fcbh pr2 timer2 period register 1111 1111 1111 1111 fcah t2con ? toutps3 toutps2 toutps1 toutps0 tmr2on t2ckps1 t2c kps0 -000 0000 -000 0000 fc9h sspbuf ssp receive buffer/transmit register xxxx xxxx uuuu uuuu fc8h sspadd ssp address register in i 2 c slave mode. ssp baud rate reload register in i 2 c master mode 0000 0000 0000 0000 fc7h sspstat smp cke d/a psr/w ua bf 0000 0000 0000 0000 fc6h sspcon1 wcol sspov sspen ckp sspm3 sspm2 sspm1 sspm0 0000 0000 0000 0000 fc5h sspcon2 gcen ackstat ackdt acken rcen pen rsen sen 0000 0000 0000 0000 fc4h adresh a/d result register high byte xxxx xxxx uuuu uuuu fc3h adresl a/d result register low byte xxxx xxxx uuuu uuuu fc2h adcon0 ? ? chs3 chs2 chs1 chs0 go/done adon --00 0000 --00 0000 fc1h adcon1 ? ? vcfg1 vcfg0 pcfg3 pcfg2 pcfg1 pcfg0 --00 0000 --00 0000 fc0h adcon2 adfm ? ? ? ? adcs2 adcs1 adcs0 0--- -000 0--- -000 fbfh ccpr1h capture/compare/pwm register1 high byte xxxx xxxx uuuu uuuu fbeh ccpr1l capture/compare/pwm register1 low byte xxxx xxxx uuuu uuuu fbdh ccp1con ? ? dc1b1 dc1b0 ccp1m3 ccp1m2 ccp1m1 ccp1m0 --00 0000 --00 0000 fbch ccpr2h capture/compare/pwm register2 high byte xxxx xxxx uuuu uuuu fbbh ccpr2l capture/compare/pwm register2 low byte xxxx xxxx uuuu uuuu fbah ccp2con ? ? dc2b1 dc2b0 ccp2m3 ccp2m2 ccp2m1 ccp2m0 --00 0000 --uu uuuu fb9h reserved rrrr rrrr rrrr rrrr fb8h reserved rrrr rrrr rrrr rrrr fb7h reserved rrrr rrrr rrrr rrrr fb6h fb5h fb4h fb3h tmr3h timer3 register high byte xxxx xxxx uuuu uuuu fb2h tmr3l timer3 register low byte xxxx xxxx uuuu uuuu fb1h t3con rd16 t3ccp2 t3ckps1 t3ckps0 t3ccp1 t3sync tmr3cs tmr3on 0000 0000 uuuu uuuu table 4-2: register file summary - PIC18C601/801 (continued) file name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por value on all other resets (1) legend x = unknown, u = unchanged, - = unimplemented, q = value depends on condition, r = reserved note 1: other (non-power-up) resets include external reset through mclr and watchdog timer reset. 2: these registers can only be modified when the combination lock is open. 3: these registers are available on pic18c801 only.
PIC18C601/801 ds39541a-page 56 advance information ? 2001 microchip technology inc. fb0h pspcon ? ? ? ? ? ? cmlk1 cmlk0 ---- --00 ---- --00 fafh spbrg usart baud rate generator 0000 0000 0000 0000 faeh rcreg usart receive register 0000 0000 0000 0000 fadh txreg usart transmit register 0000 0000 0000 0000 fach txsta csrc tx9 txen sync ? brgh trmt tx9d 0000 -010 0000 -010 fabh rcsta spen rx9 sren cren aden ferr oerr rx9d 0000 000x 0000 000x faah fa9h fa8h fa7h csel2 (2) csl7 csl6 csl5 csl4 csl3 csl2 csl1 csl0 1111 1111 uuuu uuuu fa6h cselio (2) csio7 csio6 csio5 csio4 csio3 csio2 csio1 csio0 1111 1111 uuuu uuuu fa5h fa4h fa3h fa2h ipr2 ? ? ? ? bclip lvdip tmr3ip ccp2ip ---- 1111 ---- 1111 fa1h pir2 ? ? ? ? bclif lvdif tmr3if ccp2if ---- 0000 ---- 0000 fa0h pie2 ? ? ? ? bclie lvdie tmr3ie ccp2ie ---- 0000 ---- 0000 f9fh ipr1 ? adip rcip txip sspip ccp1ip tmr2ip tmr1ip -111 1111 -111 1111 f9eh pir1 ? adif rcif txif sspif ccp1if tmr2if tmr1if -000 0000 -000 0000 f9dh pie1 ? adie rcie txie sspie ccp1ie tmr2ie tmr1ie -000 0000 -000 0000 f9ch memcon (2) ebdis pgrm wait1 wait0 ? ? wm1 wm0 0000 --00 0000 --00 f9bh f9ah trisj (3) data direction control register for portj 1111 1111 1111 1111 f99h trish (3) data direction control register for porth 1111 1111 1111 1111 f98h trisg ? ? ? read portg data latch, write portg data latch ---1 1111 ---1 1111 f96h trisf read portf data latch, write portf data latch 1111 1111 1111 1111 f96h trise data direction control register for porte 1111 1111 1111 1111 f95h trisd data direction control register for portd 1111 1111 1111 1111 f94h trisc data direction control register for portc 1111 1111 1111 1111 f93h trisb data direction control register for portb 1111 1111 1111 1111 f92h trisa ? ? data direction control register for porta --11 1111 --11 1111 f91h latj (3) read portj data latch, write portj data latch xxxx xxxx uuuu uuuu f90h lath (3) read porth data latch, write porth data latch xxxx xxxx uuuu uuuu f8fh latg ? ? ? read portg data latch, write portg data latch ---x xxxx ---u uuuu f8eh latf read portf data latch, write portf data latch xxxx xxxx uuuu uuuu f8dh late read porte data latch, write porte data latch xxxx xxxx uuuu uuuu f8ch latd read portd data latch, write portd data latch xxxx xxxx uuuu uuuu f8bh latc read portc data latch, write portc data latch xxxx xxxx uuuu uuuu f8ah latb read portb data latch, write portb data latch xxxx xxxx uuuu uuuu f89h lata ? ? read porta data latch, write porta data latch --xx xxxx --uu uuuu f88h portj (3) read portj pins, write portj data latch xxxx xxxx uuuu uuuu f87h porth (3) read porth pins, write porth data latch xxxx xxxx uuuu uuuu f86h portg ? ? ? read portg pins, write portg data latch ---x xxxx ---u uuuu f85h portf read portf pins, write portf data latch xxxx xx00 uuuu uu00 table 4-2: register file summary - PIC18C601/801 (continued) file name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por value on all other resets (1) legend x = unknown, u = unchanged, - = unimplemented, q = value depends on condition, r = reserved note 1: other (non-power-up) resets include external reset through mclr and watchdog timer reset. 2: these registers can only be modified when the combination lock is open. 3: these registers are available on pic18c801 only.
? 2001 microchip technology inc. advance information ds39541a-page 57 PIC18C601/801 f84h porte read porte pins, write porte data latch xxxx xxxx uuuu uuuu f83h portd read portd pins, write portd data latch xxxx xxxx uuuu uuuu f82h portc read portc pins, write portc data latch xxxx xxxx uuuu uuuu f81h portb read portb pins, write portb data latch xxxx xxxx uuuu uuuu f80h porta ? ? read porta pins, write porta data latch --0x 0000 --0u 0000 table 4-2: register file summary - PIC18C601/801 (continued) file name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por value on all other resets (1) legend x = unknown, u = unchanged, - = unimplemented, q = value depends on condition, r = reserved note 1: other (non-power-up) resets include external reset through mclr and watchdog timer reset. 2: these registers can only be modified when the combination lock is open. 3: these registers are available on pic18c801 only.
PIC18C601/801 ds39541a-page 58 advance information ? 2001 microchip technology inc. 4.10 access bank the access bank is an architectural enhancement that is very useful for c compiler code optimization. the techniques used by the c compiler are also useful for programs written in assembly. this data memory region can be used for: intermediate computational values local variables of subroutines faster context saving/switching of variables common variables faster evaluation/control of sfr ? s (no banking) the access bank is comprised of the upper 128 bytes in bank 15 (sfr ? s) and the lower 128 bytes in bank 0. these two sections will be referred to as access bank high and access bank low, respectively. figure 4-8 indicates the access bank areas. a bit in the instruction word specifies if the operation is to occur in the bank specified by the bsr register, or in the access bank. when forced in the access bank (a = ? 0 ? ), the last address in access bank low is followed by the first address in access bank high. access bank high maps all special function registers so that these registers can be accessed without any software overhead. 4.11 bank select register (bsr) the need for a large general purpose memory space dictates a ram banking scheme. when using direct addressing, the bsr should be configured for the desired bank. bsr<3:0> holds the upper 4 bits of the 12-bit ram address. the bsr<7:4> bits will always read ? 0 ? s, and writes will have no effect. a movlb instruction has been provided in the instruc- tion set to assist in selecting banks. if the currently selected bank is not implemented, any read will return all '0's and all writes are ignored. the status register bits will be set/cleared as appropriate for the instruction performed. each bank extends up to 0ffh (256 bytes). all data memory is implemented as static ram. a movff instruction ignores the bsr, since the 12-bit addresses are embedded into the instruction word. section 4.12 provides a description of indirect address- ing, which allows linear addressing of the entire ram space. figure 4-10: direct addressing note 1: for register file map detail, see table 4-2. 2: the access bit of the instruction can be used to force an override of the selected bank (bsr<3:0>) to the registers of the access bank. 3: the movff instruction embeds the entire 12-bit address in the instruction. data memory (1) direct addressing bank select (2) location select (3) bsr<3:0> 7 0 from opcode (3) 00h 01h 0eh 0fh bank 0 bank 1 bank 14 bank 15 1ffh 100h 0ffh 000h effh e00h fffh f00h
? 2001 microchip technology inc. advance information ds39541a-page 59 PIC18C601/801 4.12 indirect addressing, indf and fsr registers indirect addressing is a mode of addressing data mem- ory, where the data memory address in the instruction is not fixed. a sfr register is used as a pointer to the data memory location that is to be read or written. since this pointer is in ram, the contents can be modified by the program. this can be useful for data tables in the data memory and for software stacks. figure 4-11 shows the operation of indirect addressing. this shows the moving of the value to the data memory address specified by the value of the fsr register. indirect addressing is possible by using one of the indfn (0 n 2) registers. any instruction using the indfn register actually accesses the register indicated by the file select register, fsrn (0 n 2). reading the indfn register itself indirectly (fsrn = ? 0 ? ), will read 00h. writing to the indfn register indirectly, results in a no-operation. the fsrn register contains a 12-bit address, which is shown in figure 4-11. example 4-6 shows a simple use of indirect addressing to clear the ram in bank 1 (locations 100h-1ffh) in a minimum number of instructions. example 4-6: how to clear ram (bank 1) using indirect addressing there are three indirect addressing registers. to address the entire data memory space (4096 bytes), these registers are 12-bit wide. to store the 12-bits of addressing information, two 8-bit registers are required. these indirect addressing registers are: 1. fsr0: composed of fsr0h:fsr0l 2. fsr1: composed of fsr1h:fsr1l 3. fsr2: composed of fsr2h:fsr2l in addition, there are registers indf0, indf1 and indf2, which are not physically implemented. reading or writing to these registers activates indirect address- ing, with the value in the corresponding fsr register being the address of the data. if an instruction writes a value to indf0, the value will be written to the address indicated by fsr0h:fsr0l. a read from indf1 reads the data from the address indicated by fsr1h:fsr1l. indfn can be used in code anywhere an operand can be used. if indf0, indf1, or indf2 are read indirectly via an fsr, all ? 0 ? s are read (zero bit is set). similarly, if indf0, indf1, or indf2 are written to indirectly, the operation will be equivalent to a nop instruction and the status bits are not affected. 4.12.1 indirect addressing operation each fsr register has an indf register associated with it, plus four additional register addresses. perform- ing an operation on one of these five registers deter- mines how the fsr will be modified during indirect addressing. when data access is done to one of the five indfn locations, the address selected will configure the fsrn register to: do nothing to fsrn after an indirect access (no change) - indfn auto-decrement fsrn after an indirect access (post-decrement) - postdecn auto-increment fsrn after an indirect access (post-increment) - postincn auto-increment fsrn before an indirect access (pre-increment) - preincn use the value in the wreg register as an offset to fsrn. do not modify the value of the wreg or the fsrn register after an indirect access (no change) - pluswn when using the auto-increment or auto-decrement fea- tures, the effect on the fsr is not reflected in the status register. for example, if the indirect address causes the fsr to equal '0', the z bit will not be set. incrementing or decrementing an fsr affects all 12 bits. that is, when fsrnl overflows from an increment, fsrnh will be incremented automatically. adding these features allows the fsrn to be used as a software stack pointer, in addition to its uses for table operations in data memory. each fsr has an address associated with it that per- forms an indexed indirect access. when a data access to this indfn location (pluswn) occurs, the fsrn is configured to add the 2 ? s complement value in the wreg register and the value in fsr to form the address before an indirect access. the fsr value is not changed. if an indirect addressing operation is done where the target address is an fsrnh or fsrnl register, the write operation will dominate over the pre- or post- increment/decrement functions. lfsr fsr0, 100h ; nextclrf postinc0 ; clear indf ; register ; & inc pointer btfss fsr0h, 1 ; all done ; with bank1? bra next ; no, clear next continue; : ; yes, continue
PIC18C601/801 ds39541a-page 60 advance information ? 2001 microchip technology inc. figure 4-11: indirect addressing note 1: for register file map detail, see table 4-2. data memory (1) indirect addressing fsr register 11 8 7 0 0fffh 0000h location select fsrnh fsrnl
? 2001 microchip technology inc. advance information ds39541a-page 61 PIC18C601/801 4.13 status register the status register, shown in register 4-3, contains the arithmetic status of the alu. the status register can be the destination for any instruction, as with any other register. if the status register is the destination for an instruction that affects the z, dc, c, ov, or n bits, then the write to these five bits is disabled. these bits are set or cleared according to the device logic. there- fore, the result of an instruction with the status regis- ter as destination may be different than intended. for example, clrf status will clear all implemented bits and set the z bit. this leaves the status register as ---0 0100 (where - = unimplemented). it is recommended, therefore, that only bcf, bsf, swapf, movff and movwf instructions are used to alter the status register, because these instructions do not affect the z, c, dc, ov, or n bits from the status register. for other instructions which do not affect the status bits, see table 20-2. register 4-3: status register note: the c and dc bits operate as a borrow and digit borrow bit respectively, in subtraction. u-0 u-0 u-0 r/w-x r/w-x r/w-x r/w-x r/w-x ? ? ? novzdcc bit 7 bit 0 bit 7-5 unimplemented: read as '0' bit 4 n: negative bit this bit is used for signed arithmetic (2 ? s complement). it indicates whether the result of the alu operation was negative (alu msb = 1). 1 = result was negative 0 = result was positive bit 3 ov: overflow bit this bit is used for signed arithmetic (2 ? s complement). it indicates an overflow of the 7-bit magnitude, which causes the sign bit (bit 7) to change state. 1 = overflow occurred for signed arithmetic (in this arithmetic operation) 0 = no overflow occurred bit 2 z: zero bit 1 = the result of an arithmetic or logic operation is zero 0 = the result of an arithmetic or logic operation is not zero bit 1 dc: digit carry/borrow bit for arithmetic addition and subtraction instructions 1 = a carry-out from the 4th low order bit of the result occurred 0 = no carry-out from the 4th low order bit of the result note: for borrow, the polarity is reversed. a subtraction is executed by adding the two ? s complement of the second operand. for rotate ( rrcf, rrncf, rlcf, and rlncf ) instructions, this bit is loaded with either the bit 4, or bit 3 of the source register. bit 0 c: carry/borrow bit for arithmetic addition and subtraction instructions 1 = a carry-out from the most significant bit of the result occurred 0 = no carry-out from the most significant bit of the result occurred note: for borrow, the polarity is reversed. a subtraction is executed by adding the two ? s complement of the second operand. for rotate ( rrcf, rlcf ) instructions, this bit is loaded with either the high, or low order bit of the source register. legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown
PIC18C601/801 ds39541a-page 62 advance information ? 2001 microchip technology inc. 4.14 rcon register the reset control (rcon) register contains flag bits that allow differentiation between the sources of a device reset. these flags include the to , pd , por and ri bits. this register is readable and writable. register 4-4: rcon register note: it is recommended that the por bit be set after a power-on reset has been detected, so that subsequent power-on resets may be detected. r/w-0 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-0 u-0 ipen r ? ri to pd por r bit 7 bit 0 bit 7 ipen: interrupt priority enable bit 1 = enable priority levels on interrupts 0 = disable priority levels on interrupts (16cxxx compatibility mode) bit 6 reserved: maintain as ? 0 ? bit 5 unimplemented: read as '0' bit 4 ri : reset instruction flag bit 1 = the reset instruction was not executed 0 = the reset instruction was executed causing a device reset (must be set in software after reset instruction was executed) bit 3 to : watchdog time-out flag bit 1 = after power-up, clrwdt instruction, or sleep instruction 0 = a wdt time-out occurred bit 2 pd : power-down detection flag bit 1 = after power-up or by the clrwdt instruction 0 = by execution of the sleep instruction bit 1 por : power-on reset status bit 1 = a power-on reset has not occurred 0 = a power-on reset occurred (must be set in software after a power-on reset occurs) bit 0 reserved: maintain as ? 0 ? legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown r = reserved
? 2001 microchip technology inc. advance information ds39541a-page 63 PIC18C601/801 5.0 external memory interface the external memory interface is a feature of the PIC18C601/801 that allows the processor to access external memory devices, such as flash, eprom, sram, etc. memory mapped peripherals may also be accessed. the external memory interface physical implementa- tion includes up to 26 pins on the PIC18C601 and up to 38 pins on the pic18c801. these pins are reserved for external address/data bus functions. these pins are multiplexed with i/o port pins, but the i/o functions are only enabled when program execution takes place in internal boot ram and the ebdis bit in the memcon register is set (see register 5-1). 5.1 memory control register (memcon) register 5-1 shows the memory control register (memcon). this register contains bits used to control the operation of the external memory interface. register 5-1: memcon register r/w-0 r/w-0 r/w-0 r/w-0 u-0 u-0 r/w-0 r/w-0 ebdis pgrm wait1 wait0 ? ? wm1 wm0 bit7 bit0 bit 7 ebdis : external bus disable 1 = external system bus disabled, all external bus drivers are mapped as i/o ports 0 = external system bus enabled, and i/o ports are disabled bit 6 pgrm : program ram enable 1 = 512 bytes of internal ram enabled as internal program memory from location 1ffe00h to 1fffffh, external program memory at these locations is unused. internal gpr memory from 400h to 5ffh is disabled and returns 00h. 0 = internal ram enabled as internal gpr memory from 400h to 5ffh. program memory from location 1ffe00h to 1fffffh is configured as external program memory. bit 5-4 wait<1:0> : table reads and writes bus cycle wait count 11 = table reads and writes will wait 0 t cy 10 = table reads and writes will wait 1 t cy 01 = table reads and writes will wait 2 t cy 00 = table reads and writes will wait 3 t cy bit 3-2 unimplemented : read as '0' bit 1-0 wm<1:0> : tablwt operation with 16-bit bus 1x = word write mode: tablat0 and tablat1 word output, wrh active when tablat1 written 01 = byte select mode: tablat data copied on both ms and ls byte, wrh and (ub or lb ) will activate 00 = byte write mode: tablat data copied on both ms and ls byte, wrh or wrl will activate legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown
PIC18C601/801 ds39541a-page 64 advance information ? 2001 microchip technology inc. 5.2 8-bit mode the external memory interface can operate in 8-bit mode. the mode selection is not software configurable, but is programmable via the configuration bits. there are two types of connections in 8-bit mode. they are referred to as: 8-bit multiplexed 8-bit de-multiplexed 5.2.1 8-bit multiplexed mode the 8-bit multiplexed mode applies only to the PIC18C601. data and address lines are multiplexed on port pins and must be decoded with glue logic. for 8-bit multiplexed mode on the PIC18C601, the instructions will be fetched as two 8-bit bytes on a shared data/address bus (portd). the two bytes are sequentially fetched within one instruction cycle (t cy ). therefore, the designer must choose external memory devices according to timing calculations based on 1/2 tcy (2 times instruction rate). for proper memory speed selection, glue logic propagation delay times must be considered along with setup and hold times. the address latch enable (ale) pin indicates that the address bits a<7:0> are available on the external memory interface bus. the oe output enable signal will enable one byte of program memory for a portion of the instruction cycle, then ba0 will change and the second byte will be enabled to form the 16-bit instruction word. the least significant bit of the address, ba0, must be connected to the memory devices in this mode. figure 5-1 shows an example of 8-bit multiplexed mode on the PIC18C601. the control signals used in 8-bit multiplexed mode are outlined in table 5-1. register 5-2 describes 8-bit multiplexed mode timing. figure 5-1: 8-bit multiplexed mode example table 5-1: 8-bit multiplexed mode control signals ad<7:0> PIC18C601 ba0 oe wrl 373 a d<7:0> oe wr (2) ce ale d<7:0> a<17:0> note 1: this signal only applies to table writes. see section 6.0, table reads and writes. a16, ad<15:8> cs1 a0 name 8-bit mux mode function rg0/ale ale address latch enable (ale) control pin rg1/oe oe output enable (oe ) control pin rg2/wrl wrl write low (wrl ) control pin rg4/ba0 ba0 byte address bit 0 rf3/csio csio chip select i/o (see section 5.4) rf5/cs1 cs1 chip select 1 (see section 5.4)
? 2001 microchip technology inc. advance information ds39541a-page 65 PIC18C601/801 figure 5-2: 8-bit multiplexed mode timing 5.2.2 8-bit de-multiplexed mode the 8-bit de-multiplexed mode applies only to the pic18c801. data and address lines are available sep- arately. external components are not necessary in this mode. for 8-bit de-multiplexed mode on the pic18c801, the instructions are fetched as two 8-bit bytes on a dedi- cated data bus (portj). the address will be pre- sented for the entire duration of the fetch cycle on a separate address bus. the two instruction bytes are sequentially fetched within one instruction cycle (t cy ). therefore, the designer must choose external memory devices according to timing calculations, based on 1/2 t cy (2 times instruction rate). for proper memory speed selection, setup and hold times must be considered. the address latch enable (ale) pin is left uncon- nected, since glue logic is not necessary. the oe out- put enable signal will enable one byte of program memory for a portion of the instruction cycle, then ba0 will change and the second byte will be enabled to form the 16-bit instruction word. the least significant bit of the address, ba0, must be connected to the memory devices in this mode. figure 5-3 shows an example of 8-bit de-multiplexed mode on the pic18c801. the control signals used in 8-bit de-multiplexed mode are outlined in register 5-2. register 5-4 describes 8-bit de-multiplexed mode timing. a16, ad<15:8> ale oe ad<7:0> ba0 opcode fetch movlw 55h from 007556h q1 q2 q3 q4 03ah abh 55h 0eh
PIC18C601/801 ds39541a-page 66 advance information ? 2001 microchip technology inc. figure 5-3: 8-bit de-multiplexed mode example table 5-2: 8-bit de-multiplexed mode control signals figure 5-4: 8-bit de-multiplexed mode timing name 8-bit de-mux mode function rg0/ale ale address latch enable (ale) control pin rg1/oe oe output enable (oe ) control pin rg2/wrl wrl write low (wrl ) control pin rg4/ba0 ba0 byte address bit 0 rf3/csio csio chip select i/o (see section 5.4) rf4/cs2 cs2 chip select 2 (see section 5.4) rf5/cs1 cs1 chip select 1 (see section 5.4) d<7:0> pic18c801 ba0 oe wrl ale a<19:16>, ad<15:0> cs1 a d<7:0> oe wr (1) ce d<7:0> a<20:0> note 1: this signal only applies to table writes. see section 6.0, table reads and writes. a0 a16, ad<15:8> ale oe ad<7:0> ba0 opcode fetch movlw 55h from 007556h q1 q2 q3 q4 03ah 55h 0eh
? 2001 microchip technology inc. advance information ds39541a-page 67 PIC18C601/801 5.3 16-bit mode the external memory interface can operate in 16-bit mode. the mode selection is not software configurable, but is programmable via the configuration bits. the wm<1:0> bits in the memcon register determine three types of connections in 16-bit mode. they are referred to as: 16-bit byte write 16-bit word write 16-bit byte select these three different configurations allow the designer maximum flexibility in using 8-bit and 16-bit memory devices. for all 16-bit modes, the address latch enable (ale) pin indicates that the address bits a<15:0> are avail- able on the external memory interface bus. following the address latch, the output enable signal (oe ) will enable both bytes of program memory at once to form a 16-bit instruction word. in byte select mode, jedec standard flash memo- ries will require ba0 for the byte address line, and one i/o line, to select between byte and word mode. the other 16-bit modes do not need ba0. jedec standard static ram memories will use the ub or ul signals for byte selection. 5.3.1 16-bit byte write mode figure 5-5 shows an example of 16-bit byte write mode for the PIC18C601/801. figure 5-5: 16-bit byte write mode example ad<15:8> a<19:16> ale d<7:0> 373 a d<7:0> a<19:0> a d<7:0> 373 oe wrh oe oe wr (1) wr (1) ce ce note 1: this signal only applies to table writes. see section 6.0, table reads and writes. wrl d<15:8> (lsb) (msb) pic18c801 d<7:0> ad<7:0> cs1
PIC18C601/801 ds39541a-page 68 advance information ? 2001 microchip technology inc. 5.3.2 16-bit word write mode figure 5-6 shows an example of 16-bit word write mode for the pic18c801. figure 5-6: 16-bit word write mode example 5.3.3 16-bit byte select mode figure 5-7 shows an example of 16-bit byte select mode for the pic18c801. figure 5-7: 16-bit byte select mode example ad<7:0> pic18c801 ad<15:8> ale 373 a<20:1> 373 o e w rh note 1: this signal only applies to table writes. see section 6.0, table reads and writes. a<19:16> a d<15:0> oe wr (1) ce d<15:0> jedec word eprom memory cs1 ad<7:0> pic18c801 ad<15:8> ale 373 a<20:1> 373 o e w rh note 1: this signal only applies to table writes. see section 6.0, table reads and writes. a<19:16> w rl ba0 jedec word a d<15:0> a<20:1> ce d<15:0> i/o oe wr (1) a0 byte/word flash memory jedec word a d<15:0> ce d<15:0> oe wr (1) lb ub sram memory lb ub cs1 cs2
? 2001 microchip technology inc. advance information ds39541a-page 69 PIC18C601/801 5.3.4 16-bit mode control signals table 5-3 describes the 16-bit mode control signals for the PIC18C601/801. table 5-3: PIC18C601/801 16-bit mode control signals 5.3.5 16-bit mode timing figure 5-8 describes the 16-bit mode timing for the PIC18C601/801. figure 5-8: 16-bit mode timing name 18c601 16-bit mode 18c801 16-bit mode function rg0/ale ale ale address latch enable (ale) control pin rg1/oe oe oe output enable (oe ) control pin rg2/wrl wrl wrl write low (wrl ) control pin rg3/wrh wrh wrh write high (wrh ) control pin rg4/ba0 ba0 ba0 byte address bit 0 rf3/csio csio csio chip select i/o (see section 5.4) rf4/cs2 n/a cs2 chip select 2 (see section 5.4) rf5/cs1 cs1 cs1 chip select 1 (see section 5.4) rf6/ub ub ub upper byte enable (ub ) control pin rf7/lb lb lb lower byte enable (lb ) control pin i/o i/o i/o i/o as byte/word control pin for jedec flash a16, ad<15:8> ale oe ad<7:0> ba0 opcode fetch movlw 55h from 007556h q1 q2 q3 q4 03ah 0e55h 3aabh wrh wrl ? 1 ? ? 1 ?
PIC18C601/801 ds39541a-page 70 advance information ? 2001 microchip technology inc. 5.4 chip selects chip select signals are used to select regions of exter- nal memory and i/o devices for access. the pic18c801 has three chip selects and all are program- mable. the chip select signals are cs1 , cs2 and csio . cs1 and cs2 are general purpose chip selects that are used to enable large portions of program mem- ory. csio is used to enable external i/o expansion. the PIC18C601uses two of these programmable chip selects: cs1 and csio . two sfrs are used to control the chip select signals. these are csel2 and cselio (see register 5-2 and register 5-3). a chip select signal is asserted low when the cpu makes an access to a dedicated range of addresses specified in the chip select registers, csel2 and cselio. the 8-bit value found in either of these registers is decoded as one of 256, 8k banks of pro- gram memory. if both chip select registers are 00h, all of the chip select signals are disabled and their corre- sponding pins are configured as i/o. since the last 512 bytes of program memory are dedicated to internal pro- gram ram, the chip select signals will not activate if the program memory address falls in this range. register 5-2: csel2 register register 5-3: cselio register r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 csl7 csl6 csl5 csl4 csl3 csl2 csl1 csl0 bit 7 bit 0 bit 7-0 csl<7:0> : chip select 2 address decode bits xxh = all eight bits are compared to the most significant bits pc<20:13> of the program counter. if pc<20:13> csl<7:0> register, then the cs2 signal is low. if pc<20:13> < csl<7:0>, cs2 is high. 00h =cs2 is inactive legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 csio7 csio6 csio5 csio4 csio3 csio2 csio1 csio0 bit7 bit0 bit 7-0 csio<7:0> : chip select io address decode bits xxh = all eight bits are compared to the most significant bits pc<20:13> of the program counter. if pc<20:13> = csio<7:0>, then the csio signal is low. if not, csio is high. 00h =csio is inactive legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown
? 2001 microchip technology inc. advance information ds39541a-page 71 PIC18C601/801 5.4.1 chip select 1 (cs1 ) cs1 is enabled by writing a value other than 00h into either the csel2 register, or the cselio register. if both of the chip select registers are programmed to 00h, the cs1 signal is not enabled and the rf5 pin is configured as i/o. cs1 is low for all addresses in which cs2 and cselio are high. therefore, if csel2 = 20h and cselio = 80h, then the cs1 signal will be low for the address that falls between 000000h and (2000h x 20h) - 1 = 03ffffh. cs1 will always be low for the lower 8k of program memory. figure 5-9 shows an example address map for cs1 . 5.4.2 chip select 2 (cs2 ) cs2 is enabled for program memory accesses, starting at the address derived by the 8-bit value contained in csel2. for example, if the value contained in the csel2 register is 80h, then the cs2 signal will be asserted low whenever the address is greater than or equal to 2000h x 80h = 100000h. a 00h value in the csel2 register will disable the cs2 signal and will configure the rf4 pin as i/o. figure 5-9 shows an example address map for cs2 . 5.4.3 chip select i/o (csio ) csio is enabled for a fixed 8k address range starting at the address defined by the 8-bit value contained in cselio. if, for instance, the value contained in the cselio register is 80h, then the csio signal will be low for the address range between 100000h and 101fffh. if the 8k address block overlaps the address range specified in the csel2 register, the csio signal will be low, and the cs2 signal will be high, for that region. a 00h value in the cselio register will disable the csio signal and will configure the rf3 pin as i/o. figure 5-9 shows an example address map for csio . figure 5-9: example configuration address map for cs1 , cs2 , and csio program memory csel2 = ffh (default) cselio = ffh (default) = cs1 active = cs2 active = csio active 000000h 1fffffh program memory csel2 = 80h cselio = 00h 000000h 1fffffh program memory csel2 = 20h cselio = 80h 000000h 1fffffh 100000h 0fffffh 100000h 101fffh 102000h 0fffffh 03ffffh 040000h = no chip select active internal execution if pgrm = 1 1ffdffh 1ffe00h 1ffdffh 1ffe00h 1ffdffh 1ffe00h
PIC18C601/801 ds39541a-page 72 advance information ? 2001 microchip technology inc. 5.5 external wait cycles the external memory interface supports wait cycles. wait cycles only apply to table read and table write operations over the external bus. see section 6.0 for more details. since the device execution is tied to instruction fetches, there is no need to execute faster than the fetch rate. so, if the program needs to be slowed, the processor speed must be slowed with a different t cy time.
? 2001 microchip technology inc. advance information ds39541a-page 73 PIC18C601/801 6.0 table reads/table writes PIC18C601/801 devices use two memory spaces: the external program memory space and the data memory space. table reads and table writes have been pro- vided to move data between these two memory spaces through an 8-bit register (tablat). the operations that allow the processor to move data between the data and external program memory spaces are: table read ( tblrd ) table write ( tblwt ) table read operations retrieve data from external pro- gram memory and place it into the data memory space. figure 6-1 shows the operation of a table read with program and data memory. table write operations store data from the data mem- ory space into external program memory. figure 6-2 shows the operation of a table write with external pro- gram and data memory. table operations work with byte entities. a table block containing data is not required to be word aligned, so a table block can start and end at any byte address. if a table write is being used to write an executable pro- gram to program memory, program instructions must be word aligned. figure 6-1: table read operation figure 6-2: table write operation table pointer (1) table latch (8-bit) external program memory tblptrh tblptrl tablat tblptru instruction: tblrd * note 1: table pointer points to a byte in external program memory. program memory (tblptr) table pointer (1) table latch (8-bit) external program memory tblptrh tblptrl tablat external (tblptr) tblptru instruction: tblwt * note 1: table pointer points to a byte in external program memory. program memory
PIC18C601/801 ds39541a-page 74 advance information ? 2001 microchip technology inc. 6.1 control registers several control registers are used in conjunction with the tblrd and tblwt instructions. these include: tablat register tblptr registers 6.1.1 tablat - table latch register the table latch (tablat) is an 8-bit register mapped into the sfr space. the table latch is used to hold 8-bit data during data transfers between program mem- ory and data memory. 6.1.2 tblptr - table pointer register the table pointer (tblptr) addresses a byte within the program memory. the tblptr is comprised of three sfr registers (table pointer upper byte, high byte and low byte). these three registers (tblptru:tblptrh:tblptrl) join to form a 21-bit wide pointer. the 21-bits allow the device to address up to 2 mbytes of program memory space. the table pointer tblptr is used by the tblrd and tblwrt instructions. these instructions can update the tblptr in one of four ways, based on the table operation. these operations are shown in table 6-1. these operations on the tblptr only affect the low order 21-bits. table 6-1: table pointer operations with tblrd and tblwt instructions example operation on table pointer tblrd* tblwt* tblptr is not modified tblrd*+ tblwt*+ tblptr is incremented after the read/write tblrd*- tblwt*- tblptr is decremented after the read/write tblrd+* tblwt+* tblptr is incremented before the read/write
? 2001 microchip technology inc. advance information ds39541a-page 75 PIC18C601/801 6.2 table read the tblrd instruction is used to retrieve data from external program memory and place it into data memory. tblptr points to a byte address in external program memory space. executing tblrd places the byte into tablat. in addition, tblptr can be modified auto- matically for the next table read operation. table reads from external program memory are performed one byte at a time. if the external interface is 8-bit, the bus interface circuitry in tablat will load the external value into tablat. if the external interface is 16-bit, interface circuitry in tablat will select either the high or low byte of the data from the 16-bit bus, based on the least significant bit of the address. example 6-1describes how to use tblrd . figure 6-3 and figure 6-4 show table read timings for an 8-bit external interface, and figure 6-5 describes table read timing for a 16-bit interface. example 6-1: table read code example figure 6-3: tblrd external interface timing (8-bit multiplexed mode) ; read a byte from location 0020h clrf tblptru ; clear upper 5 bits of tblptr clrf tblptrh ; clear higher 8 bits of tblptr movlw 20h ; load 20h into movwf tblptrl ; tblptrl tblrd* ; data is in tablat q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 a<15:8> ale oe aah wrh wrl ad<7:0> 03ah 03ah ba0 opcode fetch opcode fetch opcode fetch tblrd* tblrd cycle1 addlw 55h from 007554h 08h ? 1 ? q2 q1 q3 q4 ccfh 33h tablrd 92h from 199e67h 92h ? 1 ? 00h abh 55h 0eh ach 55h 0fh 03ah ? 1 ? ? 1 ? from 007558h memory cycle instruction execution inst(pc-2) tblrd cycle2 movlw 55h from 007556h movlw
PIC18C601/801 ds39541a-page 76 advance information ? 2001 microchip technology inc. figure 6-4: tblrd external interface timing (8-bit de-multiplexed mode) figure 6-5: tblrd external bus timing (16-bit mode) q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 a<15:8> ale oe wrh wrl ad<7:0> 03aaah 03aabh ba0 opcode fetch opcode fetch opcode fetch tblrd* tblrd cycle1 addlw 55h from 007554h 08h ? 1 ? q2 q1 q3 q4 ccf33h tablrd 92h from 199e67h 92h ? 1 ? 00h 55h 0eh 55h 03aach ? 1 ? ? 1 ? from 007558h memory cycle instruction execution inst(pc-2) tblrd cycle2 movlw 55h from 007556h movlw q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 a<19:16> ale oe 3aaah wrh wrl ad<15:0> 0h 0h ba0 opcode fetch opcode fetch opcode fetch tblrd* tblrd cycle1 addlw 55h from 007554h ? 1 ? q2 q1 q3 q4 ch cf33h tablrd 92h from 199e67h 9256h ? 1 ? 0008h 3aabh 0e55h 3aach 0f55h 0h ? 1 ? ? 1 ? from 007558h memory cycle instruction execution inst(pc-2) tblrd cycle2 movlw 55h from 007556h movlw
? 2001 microchip technology inc. advance information ds39541a-page 77 PIC18C601/801 6.3 table write table write operations store data from the data mem- ory space into external program memory. PIC18C601/801devices perform table writes one byte at a time. table writes to external memory are two-cycle instructions, unless wait states are enabled. the last cycle writes the data to the external memory location. 16-bit interface table writes depend on the type of external device that is connected and the wm<1:0> bits in the memcon register (see figure 5-2). example 6-2 describes how to use tblwt . example 6-2: table write code example ; write a byte to location 0020h clrf tblptru ; clear upper 5 bits of tblptr clrf tblptrh ; clear higher 8 bits of tblptr movlw 20h ; load 20h into movwf tblptrl ; tblptrl movlw 55h ; load 55h into movwf tblat ; tblat tblwt* ; write it
PIC18C601/801 ds39541a-page 78 advance information ? 2001 microchip technology inc. 6.3.1 8-bit external table writes when the external bus is 8-bit, the byte-wide table write exactly corresponds to the bus length and there are no special considerations required. the wrl signal is used as the active write signal. figure 6-6 and figure 6-7 show the timings associated with the 8-bit modes. figure 6-6: tblwt external interace timing (8-bit multiplexed mode) q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 a<19:8> ale aah wrh wrl ad<7:0> 03ah 03ah ba0 opcode fetch opcode fetch opcode fetch tblwt* tblwt cycle1 addlw 55h from 007554h 08h ? 1 ? q2 q1 q3 q4 ccfh 33h tblwt 92h to 199e67h 92h 00h abh 55h 0eh ach 55h 0fh 03ah from 007558h memory cycle instruction execution inst(pc-2) tblwt cycle2 movlw 55h from 007556h movlw oe
? 2001 microchip technology inc. advance information ds39541a-page 79 PIC18C601/801 figure 6-7: tblwt external interface timing (8-bit de-multiplexed mode) q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 a<19:8> ale oe wrh wrl ad<7:0> 03ah 03ah ba0 opcode fetch opcode fetch opcode fetch tblwt* tblwt cycle1 addlw 55h from 007554h 08h ? 1 ? q2 q1 q3 q4 ccfh tblwt 92h to 199e67h 92h 00h 55h 0eh 55h 0fh 03ah from 007558h memory cycle instruction execution inst(pc-2) tblwt cycle2 movlw 55h from 007556h movlw
PIC18C601/801 ds39541a-page 80 advance information ? 2001 microchip technology inc. 6.3.2 16-bit external table write (byte write mode) this mode allows table writes to byte-wide external memories. during a tblwt cycle, the tablat data is presented on the upper and lower byte of the ad<15:0> bus. the appropriate wrh or wrl line is strobed based on the lsb of the tblptr. figure 6-8 shows the timing associated with this mode. figure 6-8: tblwt external interface timing (16-bit byte write mode) q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 a<19:16> ale oe 3aaah wrh wrl ad<15:0> 0h 0h ba0 opcode fetch opcode fetch opcode fetch tblwt*+ tblwt* cycle1 movlw 55h from 007554h 000dh q2 q1 q3 q4 ch cf33h tblwt 56h to 199e66h 5656h 3aabh 6ff4h 3aach 000ch 0h from 00755ah memory cycle instruction execution inst(pc-2) tblwt* cycle2 movwf tablat from 007556h q2 q1 q3 q4 q2 q1 q3 q4 0h 3aadh tblwt 92h to 199e67h 0e55h cf33h 9292h ch tblwt*+ cycle1 tblwt*+ cycle2 ub lb opcode fetch tblwt* from 007558h movwf
? 2001 microchip technology inc. advance information ds39541a-page 81 PIC18C601/801 6.3.3 external table write in 16-bit word write mode this mode allows table writes to any type of word- wide external memories. this method makes a distinction between tblwt cycles to even or odd addresses. during a tblwt cycle to an even address, where tblptr<0> = 0, the tablat data is transferred to a holding latch and the external address data bus is tri- stated for the data portion of the bus cycle . no write signals are activated. during a tblwt cycle to an odd address, where tblptr<0> = 1, the tablat data is presented on the upper byte of the ad<15:0> bus. the contents of the holding latch are presented on the lower byte of the ad<15:0> bus. the wrh line is strobed for each write cycle and the wrl line is unused. the ba0 line indicates the lsb of tblptr, but it is unnecessary. the ub and lb lines are active to select both bytes. the obvious limitation to this method is that the tblwt must be done in pairs on a specific word boundary to correctly write a word location. figure 6-9 shows the timing associated with this mode. figure 6-9: tblwt external interface timing (16-bit word write mode) q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 ale oe wrh wrl ba0 opcode fetch opcode fetch opcode fetch tblwt*+ tblwt* cycle1 movlw 55h from 007554h q2 q1 q3 q4 tblwt 56h to 199e66h from 00755ah memory cycle instruction execution inst(pc-2) tblwt* cycle2 movwf tablat from 007556h q2 q1 q3 q4 q2 q1 q3 q4 tblwt 92h to 199e67h tblwt*+ cycle1 tblwt*+ cycle2 ub lb opcode fetch tblwt* from 007558h movwf ? 1 ? a<19:16> 3aaah ad<15:0> 0h 0h 000dh ch cf33h 3aabh 6ff4h 3aach 000ch 0h 0h 3aadh 0e55h cf33h 9256h ch
PIC18C601/801 ds39541a-page 82 advance information ? 2001 microchip technology inc. 6.3.4 16-bit external table write (byte select mode) this mode allows table writes to word-wide external memories that have byte selection capabilities. this generally includes word-wide flash devices and word-wide static ram devices. during a tblwt cycle, the tablat data is presented on the upper and lower byte of the ad<15:0> bus. the wrh line is strobed for each write cycle and the wrl line is unused. the ba0 or ub or ul lines are used to select the byte to be written, based on the lsb of the tblptr. jedec standard flash memories will require a i/o port line to become a byte/word input signal and will use the ba0 signal as a byte address. jedec stan- dard static ram memories will use the ub or ul sig- nals to select the byte. figure 6-10 shows the timing associated with this mode. figure 6-10: tblwt external interface timing (16-bit byte select mode) q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 ale oe wrh wrl ba0 opcode fetch opcode fetch opcode fetch tblwt*+ tblwt* cycle1 movlw 55h from 007554h q2 q1 q3 q4 tblwt 56h to 199e66h from 00755ah memory cycle instruction execution inst(pc-2) tblwt* cycle2 movwf tablat from 007556h q2 q1 q3 q4 q2 q1 q3 q4 tblwt 92h to 199e67h tblwt*+ cycle1 tblwt*+ cycle2 ub lb opcode fetch tblwt* from 007558h movwf ? 1 ? a<19:16> 3aaah ad<15:0> 0h 0h 000dh ch cf33h 5656h 3aabh 6ff4h 3aach 000ch 0h 0h 3aadh 0e55h cf33h 9292h ch
? 2001 microchip technology inc. advance information ds39541a-page 83 PIC18C601/801 6.4 long writes long writes will not be supported on the PIC18C601/801 to program flash configuration memory. the configu- ration locations can only be programmed in icsp mode. 6.5 external wait cycles the table reads and writes have the capability to insert wait states when accessing external memory. these wait states only apply to the execution of a table read or write to external memory and not to instruction fetches out of external memory. the guidelines pre- sented in section 5.0 must be followed to select the proper memory speed grade for the device operating frequency. the wait<1:0> bits in the memcon register will select 0, 1, 2, or 3 extra t cy cycles per tblrd/tbwlt cycle. the wait will occur on q4. the default setting of the wait on power-up is to assert a maximum wait of 3t cy cycles. this insures that slow memories will work in microprocessor mode immedi- ately after reset. figure 6-11 shows 8-bit external bus timing for a table read with 2 wait cycles. figure 6-12 shows 16-bit external bus timing for a table read with 1 wait cycle. figure 6-11: external interface timing (8-bit mode) q2 q1 q3 q4 q2 q1 q3 q4 q4 q4 q4 q4 a<19:8> ale oe abh ad<7:0> ccfh ba0 33h opcode fetch movlw 55h 03ah 55h 92h from 007556h 2t cy wait 0eh table read of 92h from 199e67h q4 q4 q4 q4 q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 apparent q actual q
PIC18C601/801 ds39541a-page 84 advance information ? 2001 microchip technology inc. figure 6-12: external interface timing (16-bit mode) q2 q1 q3 q4 q2 q1 q3 q4 q4 q4 q4 q4 ale oe 3aabh wrh wrl ad<15:0> ba0 cf33h opcode fetch movlw 55h from 007556h 9256h 0e55h ? 1 ? ? 1 ? ? 1 ? ? 1 ? table read of 92h from 199e67h 1t cy wait q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 apparent q actual q a<19:16> 0ch 0h
? 2001 microchip technology inc. advance information ds39541a-page 85 PIC18C601/801 7.0 8 x 8 hardware multiplier an 8 x 8 hardware multiplier is included in the alu of PIC18C601/801 devices. by making the multiply a hardware operation, it completes in a single instruction cycle. this is an unsigned multiply that gives a 16-bit result. the result is stored into the 16-bit product regis- ter pair (prodh:prodl). the multiplier does not affect any flags in the status register. making the 8 x 8 multiplier execute in a single cycle gives the following advantages: higher computational throughput reduces code size requirements for multiply algorithms the performance increase allows the device to be used in some applications previously reserved for digital signal processors. table 7-1 shows a performance comparison between enhanced devices using the single cycle hardware mul- tiply, and performing the same function without the hardware multiply. table 7-1: performance comparison routine multiply method program memory (words) cycles (max) time @ 25 mhz @ 10 mhz @ 4 mhz 8 x 8 unsigned without hardware multiply 13 69 11.0 s27.6 s 69.0 s hardware multiply 1 1 160.0 ns 400.0 ns 1.0 s 8 x 8 signed without hardware multiply 33 91 14.6 s36.4 s 91.0 s hardware multiply 6 6 960.0 ns 2.4 s 6.0 s 16 x 16 unsigned without hardware multiply 21 242 38.7 s96.8 s 242.0 s hardware multiply 24 24 3.8 s 9.6 s 24.0 s 16 x 16 signed without hardware multiply 52 254 40.6 s102.6 s 254.0 s hardware multiply 36 36 5.8 s 14.4 s 36.0 s
PIC18C601/801 ds39541a-page 86 advance information ? 2001 microchip technology inc. 7.1 operation example 7-1 shows the sequence to perform an 8 x 8 unsigned multiply. only one instruction is required when one argument of the multiply is already loaded in the wreg register. example 7-2 shows the sequence to do an 8 x 8 signed multiply. to account for the sign bits of the arguments, each argument ? s most significant bit (msb) is tested and the appropriate subtractions are done. example 7-1: 8 x 8 unsigned multiply routine example 7-2: 8 x 8 signed multiply routine example 7-3 shows the sequence to perform a 16 x 16 unsigned multiply. equation 7-1 shows the algorithm that is used. the 32-bit result is stored in 4 registers res3:res0. equation 7-1: 16 x 16 unsigned multiplication algorithm example 7-3: 16 x 16 unsigned multiply routine example 7-4 shows the sequence to perform a 16 x 16 signed multiply. equation 7-2 shows the algorithm used. the 32-bit result is stored in four registers, res3:res0. to account for the sign bits of the argu- ments, each argument pairs ? most significant bit (msb) is tested and the appropriate subtractions are done. equation 7-2: 16 x 16 signed multiplication algorithm movff arg1, wreg ; mulwf arg2 ; arg1 * arg2 -> ; prodh:prodl movff arg1, wreg mulwf arg2 ; arg1 * arg2 -> ; prodh:prodl btfsc arg2, sb ; test sign bit subwf prodh ; prodh = prodh ; - arg1 movff arg2, wreg btfsc arg1, sb ; test sign bit subwf prodh ; prodh = prodh ; - arg2 res3:res0 = arg1h:arg1l ? arg2h:arg2l = (arg1h ? arg2h ? 2 16 )+ (arg1h ? arg2l ? 2 8 )+ (arg1l ? arg2h ? 2 8 )+ (arg1l ? arg2l) movff arg1l, wreg mulwf arg2l ; arg1l * arg2l -> ; prodh:prodl movff prodh, res1 ; movff prodl, res0 ; ; movff arg1h, wreg mulwf arg2h ; arg1h * arg2h -> ; prodh:prodl movff prodh, res3 ; movff prodl, res2 ; ; movff arg1l, wreg mulwf arg2h ; arg1l * arg2h -> ; prodh:prodl movf prodl, w ; addwf res1 ; add cross movf prodh, w ; products addwfc res2 ; clrf wreg ; addwfc res3 ; ; movff arg1h, wreg ; mulwf arg2l ; arg1h * arg2l -> ; prodh:prodl movf prodl, w ; addwf res1 ; add cross movf prodh, w ; products addwfc res2 ; clrf wreg ; addwfc res3 ; res3:res0 = arg1h:arg1l ? arg2h:arg2l = (arg1h ? arg2h ? 2 16 )+ (arg1h ? arg2l ? 2 8 )+ (arg1l ? arg2h ? 2 8 )+ (arg1l ? arg2l) + (-1 ? arg2h<7> ? arg1h:arg1l ? 2 16 )+ (-1 ? arg1h<7> ? arg2h:arg2l ? 2 16 )
? 2001 microchip technology inc. advance information ds39541a-page 87 PIC18C601/801 example 7-4: 16 x 16 signed multiply routine movff arg1l, wreg mulwf arg2l ; arg1l * arg2l -> ; prodh:prodl movff prodh, res1 ; movff prodl, res0 ; ; movff arg1h, wreg mulwf arg2h ; arg1h * arg2h -> ; prodh:prodl movff prodh, res3 ; movff prodl, res2 ; ; movff arg1l, wreg mulwf arg2h ; arg1l * arg2h -> ; prodh:prodl movf prodl, w ; addwf res1 ; add cross movf prodh, w ; products addwfc res2 ; clrf wreg ; addwfc res3 ; ; movff arg1h, wreg ; mulwf arg2l ; arg1h * arg2l -> ; prodh:prodl movf prodl, w ; addwf res1 ; add cross movf prodh, w ; products addwfc res2 ; clrf wreg ; addwfc res3 ; ; btfss arg2h, 7 ; arg2h:arg2l neg? goto sign_arg1 ; no, check arg1 movff arg1l, wreg ; subwf res2 ; movff arg1h, wreg ; subwfb res3 ; sign_arg1 btfss arg1h, 7 ; arg1h:arg1l neg? goto cont_code ; no, done movff arg2l, wreg ; subwf res2 ; movff arg2h, wreg ; subwfb res3 ; cont_code :
PIC18C601/801 ds39541a-page 88 advance information ? 2001 microchip technology inc. notes:
? 2001 microchip technology inc. advance information ds39541a-page 89 PIC18C601/801 8.0 interrupts PIC18C601/801 devices have 15 interrupt sources and an interrupt priority feature that allows each interrupt source to be assigned a high priority level, or a low pri- ority level. the high priority interrupt vector is at 000008h and the low priority interrupt vector is at 000018h. high priority interrupt events will override any low priority interrupts that may be in progress. there are 10 registers that are used to control interrupt operation. these registers are: rcon intcon intcon2 intcon3 pir1, pir2 pie1, pie2 ipr1, ipr2 it is recommended that the microchip header files sup- plied with mplab ? ide be used for the symbolic bit names in these registers. this allows the assembler/ compiler to automatically take care of the placement of these bits within the specified register. each interrupt source has three bits to control its oper- ation. the functions of these bits are: flag bit to indicate that an interrupt event occurred enable bit that allows program execution to branch to the interrupt vector address when the flag bit is set priority bit to select high priority or low priority the interrupt priority feature is enabled by setting the ipen bit (rcon register). when interrupt priority is enabled, there are two bits that enable interrupts glo- bally. setting the gieh bit (intcon register) enables all interrupts that have the priority bit set. setting the giel bit (intcon register) enables all interrupts that have the priority bit cleared. when the interrupt flag, enable bit and appropriate global interrupt enable bit are set, the interrupt will vector immediately to address 000008h or 000018h, depending on the priority level. individual interrupts can be disabled through their cor- responding enable bits. when the ipen bit is cleared (default state), the inter- rupt priority feature is disabled and interrupts are compatible with picmicro ? mid-range devices. in com- patibility mode, the interrupt priority bits for each source have no effect. the peie bit (intcon register) enables/disables all peripheral interrupt sources. the gie bit (intcon register) enables/disables all interrupt sources. all interrupts branch to address 000008h in compatibility mode. when an interrupt is responded to, the global interrupt enable bit is cleared to disable further interrupts. if the ipen bit is cleared, this is the gie bit. if interrupt prior- ity levels are used, this will be either the gieh or giel bit. high priority interrupt sources can interrupt a low priority interrupt. the return address is pushed onto the stack and the pc is loaded with the interrupt vector address (000008h or 000018h). once in the interrupt service routine, the source(s) of the interrupt can be deter- mined by polling the interrupt flag bits. the interrupt flag bits must be cleared in software before re-enabling interrupts, to avoid recursive interrupts. the "return from interrupt" instruction, retfie , exits the interrupt routine and sets the gie bit (gieh or giel if priority levels are used), which re-enables interrupts. for external interrupt events, such as the int pins or the portb input change interrupt, the interrupt latency will be three to four instruction cycles. the exact latency is the same for one or two cycle instructions. individual interrupt flag bits are set, regardless of the status of their corresponding enable bit or the gie bit.
PIC18C601/801 ds39541a-page 90 advance information ? 2001 microchip technology inc. figure 8-1: interrupt logic tmr0ie gieh/gie giel/peie wake-up if in sleep mode interrupt to cpu vector to location 0008h int2f int2e int2p int1f int1e int1p tmr0if tmr0ie tmr0ip int0f int0e rbif rbie rbip ipen tmr0if tmr0ip int1f int1e int1p int2f int2e int2p rbif rbie rbip int0f int0e giel\peie interrupt to cpu vector to location ipen ipen 0018h peripheral interrupt flag bit peripheral interrupt enable bit peripheral interrupt priority bit peripheral interrupt flag bit peripheral interrupt enable bit peripheral interrupt priority bit tmr1if tmr1ie tmr1ip xxxxif xxxxie xxxxip additional peripheral interrupts tmr1if tmr1ie tmr1ip high priority interrupt generation low priority interrupt generation xxxxif xxxxie xxxxip additional peripheral interrupts
? 2001 microchip technology inc. advance information ds39541a-page 91 PIC18C601/801 8.1 control registers this section contains the control and status registers. 8.1.1 intcon registers the intcon registers are readable and writable registers, which contain various enable, priority, and flag bits. register 8-1: intcon register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-x gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif bit 7 bit 0 bit 7 gie/gieh: global interrupt enable bit when ipen = 0: 1 = enables all unmasked interrupts 0 = disables all interrupts when ipen = 1: 1 = enables all high priority interrupts 0 = disables all high priority interrupts bit 6 peie/giel: peripheral interrupt enable bit when ipen = 0: 1 = enables all unmasked peripheral interrupts 0 = disables all peripheral interrupts when ipen = 1: 1 = enables all low priority peripheral interrupts 0 = disables all priority peripheral interrupts bit 5 tmr0ie: tmr0 overflow interrupt enable bit 1 = enables the tmr0 overflow interrupt 0 = disables the tmr0 overflow interrupt bit 4 int0ie: int0 external interrupt enable bit 1 = enables the int0 external interrupt 0 = disables the int0 external interrupt bit 3 rbie: rb port change interrupt enable bit 1 = enables the rb port change interrupt 0 = disables the rb port change interrupt bit 2 tmr0if: tmr0 overflow interrupt flag bit 1 = tmr0 register has overflowed (must be cleared in software) 0 = tmr0 register did not overflow bit 1 int0if: int0 external interrupt flag bit 1 = the int0 external interrupt occurred (must be cleared in software) 0 = the int0 external interrupt did not occur bit 0 rbif: rb port change interrupt flag bit 1 = at least one of the rb7:rb4 pins changed state (must be cleared in software) 0 = none of the rb7:rb4 pins have changed state legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown note: interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit, or the global enable bit. user software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. this feature allows software polling.
PIC18C601/801 ds39541a-page 92 advance information ? 2001 microchip technology inc. register 8-2: intcon2 register r/w-1 r/w-1 r/w-1 r/w-1 u-0 r/w-1 u-0 r/w-1 rbpu intedg0 intedg1 intedg2 ? tmr0ip ? rbip bit 7 bit 0 bit 7 rbpu : portb pull-up enable bit 1 = all portb pull-ups are disabled 0 = portb pull-ups are enabled by individual port latch values bit 6 intedg0 : external interrupt 0 edge select bit 1 = interrupt on rising edge 0 = interrupt on falling edge bit 5 intedg1 : external interrupt 1 edge select bit 1 = interrupt on rising edge 0 = interrupt on falling edge bit 4 intedg2 : external interrupt 2 edge select bit 1 = interrupt on rising edge 0 = interrupt on falling edge bit 3 unimplemented: read as ? 0 ? bit 2 tmr0ip : tmr0 overflow interrupt priority bit 1 = high priority 0 = low priority bit 1 unimplemented: read as ? 0 ? bit 0 rbip : rb port change interrupt priority bit 1 = high priority 0 = low priority legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown note: interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit, or the global enable bit. user software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. this feature allows software polling.
? 2001 microchip technology inc. advance information ds39541a-page 93 PIC18C601/801 register 8-3: intcon3 register r/w-1 r/w-1 u-0 r/w-0 r/w-0 u-0 r/w-0 r/w-0 int2ip int1ip ? int2ie int1ie ? int2if int1if bit 7 bit 0 bit 7 int2ip: int2 external interrupt priority bit 1 = high priority 0 = low priority bit 6 int1ip: int1 external interrupt priority bit 1 = high priority 0 = low priority bit 5 unimplemented: read as ? 0 ? bit 4 int2ie: int2 external interrupt enable bit 1 = enables the int2 external interrupt 0 = disables the int2 external interrupt bit 3 int1ie: int1 external interrupt enable bit 1 = enables the int1 external interrupt 0 = disables the int1 external interrupt bit 2 unimplemented: read as ? 0 ? bit 1 int2if: int2 external interrupt flag bit 1 = the int2 external interrupt occurred (must be cleared in software) 0 = the int2 external interrupt did not occur bit 0 int1if: int1 external interrupt flag bit 1 = the int1 external interrupt occurred (must be cleared in software) 0 = the int1 external interrupt did not occur legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown note: interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit, or the global enable bit. user software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. this feature allows software polling.
PIC18C601/801 ds39541a-page 94 advance information ? 2001 microchip technology inc. 8.1.2 pir registers the peripheral interrupt request (pir) registers con- tain the individual flag bits for the peripheral interrupts (register 8-5). there are two peripheral interrupt request (flag) registers (pir1, pir2). 8.1.3 pie registers the peripheral interrupt enable (pie) registers contain the individual enable bits for the peripheral interrupts (register 8-6). there are two two peripheral interrupt enable registers (pie1, pie2). when ipen is clear, the peie bit must be set to enable any of these peripheral interrupts. 8.1.4 ipr registers the interrupt priority (ipr) registers contain the individ- ual priority bits for the peripheral interrupts (register 8-9). there are two peripheral interrupt priority registers (ipr1, ipr2). the operation of the priority bits requires that the interrupt priority enable bit (ipen) be set. 8.1.5 rcon register the reset control (rcon) register contains the bit that is used to enable prioritized interrupts (ipen). register 8-4: rcon register note 1: interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit, or the global enable bit, gie (intcon register). 2: user software should ensure the appropri- ate interrupt flag bits are cleared prior to enabling an interrupt, and after servicing that interrupt. r/w-0 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-0 u-0 ipen r ? ri to pd por r bit 7 bit 0 bit 7 ipen: interrupt priority enable bit 1 = enable priority levels on interrupts 0 = disable priority levels on interrupts (16cxxx compatibility mode) bit 6 reserved: maintain as '0' bit 5 unimplemented: read as '0' bit 4 ri : reset instruction flag bit for details of bit operation, see register 4-4 bit 3 to : watchdog time-out flag bit for details of bit operation, see register 4-4 bit 2 pd : power-down detection flag bit for details of bit operation, see register 4-4 bit 1 por : power-on reset status bit for details of bit operation, see register 4-4 bit 0 reserved: maintain as '0' legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown
? 2001 microchip technology inc. advance information ds39541a-page 95 PIC18C601/801 register 8-5: pir1 register u-0 r/w-0 r-0 r-0 r/w-0 r/w-0 r/w-0 r/w-0 ? adif rcif txif sspif ccp1if tmr2if tmr1if bit 7 bit 0 bit 7 unimplemented: read as ? 0 ? bit 6 adif : a/d converter interrupt flag bit 1 = an a/d conversion completed (must be cleared in software) 0 = the a/d conversion is not complete bit 5 rcif : usart receive interrupt flag bit 1 = the usart receive buffer, rcreg, is full (cleared when rcreg is read) 0 = the usart receive buffer is empty bit 4 txif : usart transmit interrupt flag bit 1 = the usart transmit buffer, txreg, is empty (cleared when txreg is written) 0 = the usart transmit buffer is full bit 3 sspif : master synchronous serial port interrupt flag bit 1 = the transmission/reception is complete (must be cleared in software) 0 = waiting to transmit/receive bit 2 ccp1if : ccp1 interrupt flag bit capture mode : 1 = a tmr1 register capture occurred (must be cleared in software) 0 = no tmr1 register capture occurred compare mode : 1 = a tmr1 register compare match occurred (must be cleared in software) 0 = no tmr1 register compare match occurred pwm mode : unused in this mode bit 1 tmr2if: tmr2 to pr2 match interrupt flag bit 1 = tmr2 to pr2 match occurred (must be cleared in software) 0 = no tmr2 to pr2 match occurred bit 0 tmr1if: tmr1 overflow interrupt flag bit 1 = tmr1 register overflowed (must be cleared in software) 0 = tmr1 register did not overflow legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown
PIC18C601/801 ds39541a-page 96 advance information ? 2001 microchip technology inc. register 8-6: pir2 register u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? ? bclif lvdif tmr3if ccp2if bit 7 bit 0 bit 7-4 unimplemented: read as ? 0 ? bit 3 bclif: bus collision interrupt flag bit 1 = a bus collision occurred (must be cleared in software) 0 = no bus collision occurred bit 2 lvdif: low voltage detect interrupt flag bit 1 = a low voltage condition occurred (must be cleared in software) 0 = the device voltage is above the low voltage detect trip point bit 1 tmr3if: tmr3 overflow interrupt flag bit 1 = tmr3 register overflowed (must be cleared in software) 0 = tmr3 register did not overflow bit 0 ccp2if: ccpx interrupt flag bit capture mode : 1 = a tmr1 register capture occurred (must be cleared in software) 0 = no tmr1 register capture occurred compare mode : 1 = a tmr1 register compare match occurred (must be cleared in software) 0 = no tmr1 register compare match occurred pwm mode : unused in this mode legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown
? 2001 microchip technology inc. advance information ds39541a-page 97 PIC18C601/801 register 8-7: pie1 register u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? adie rcie txie sspie ccp1ie tmr2ie tmr1ie bit 7 bit 0 bit 7 unimplemented: read as ? 0 ? bit 6 adie : a/d converter interrupt enable bit 1 = enables the a/d interrupt 0 = disables the a/d interrupt bit 5 rcie : usart receive interrupt enable bit 1 = enables the usart receive interrupt 0 = disables the usart receive interrupt bit 4 txie : usart transmit interrupt enable bit 1 = enables the usart transmit interrupt 0 = disables the usart transmit interrupt bit 3 sspie : master synchronous serial port interrupt enable bit 1 = enables the mssp interrupt 0 = disables the mssp interrupt bit 2 ccp1ie : ccp1 interrupt enable bit 1 = enables the ccp1 interrupt 0 = disables the ccp1 interrupt bit 1 tmr2ie : tmr2 to pr2 match interrupt enable bit 1 = enables the tmr2 to pr2 match interrupt 0 = disables the tmr2 to pr2 match interrupt bit 0 tmr1ie : tmr1 overflow interrupt enable bit 1 = enables the tmr1 overflow interrupt 0 = disables the tmr1 overflow interrupt legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown
PIC18C601/801 ds39541a-page 98 advance information ? 2001 microchip technology inc. register 8-8: pie2 register u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? ? bclie lvdie tmr3ie ccp2ie bit 7 bit 0 bit 7-4 unimplemented: read as '0' bit 3 bclie : bus collision interrupt enable bit 1 = enabled 0 = disabled bit 2 lvdie : low voltage detect interrupt enable bit 1 = enabled 0 = disabled bit 1 tmr3ie : tmr3 overflow interrupt enable bit 1 = enables the tmr3 overflow interrupt 0 = disables the tmr3 overflow interrupt bit 0 ccp2ie : ccp2 interrupt enable bit 1 = enables the ccp2 interrupt 0 = disables the ccp2 interrupt legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown
? 2001 microchip technology inc. advance information ds39541a-page 99 PIC18C601/801 register 8-9: ipr1 register u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ? adip rcip txip sspip ccp1ip tmr2ip tmr1ip bit 7 bit 0 bit 7 unimplemented: read as ? 0 ? bit 6 adip : a/d converter interrupt priority bit 1 = high priority 0 = low priority bit 5 rcip : usart receive interrupt priority bit 1 = high priority 0 = low priority bit 4 txip : usart transmit interrupt priority bit 1 = high priority 0 = low priority bit 3 sspip : master synchronous serial port interrupt priority bit 1 = high priority 0 = low priority bit 2 ccp1ip : ccp1 interrupt priority bit 1 = high priority 0 = low priority bit 1 tmr2ip : tmr2 to pr2 match interrupt priority bit 1 = high priority 0 = low priority bit 0 tmr1ip : tmr1 overflow interrupt priority bit 1 = high priority 0 = low priority legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown
PIC18C601/801 ds39541a-page 100 advance information ? 2001 microchip technology inc. register 8-10: ipr2 register u-0 u-0 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 ? ? ? ? bclip lvdip tmr3ip ccp2ip bit 7 bit 0 bit 7-4 unimplemented: read as '0' bit 3 bclip : bus collision interrupt priority bit 1 = high priority 0 = low priority bit 2 lvdip : low voltage detect interrupt priority bit 1 = high priority 0 = low priority bit 1 tmr3ip : tmr3 overflow interrupt priority bit 1 = high priority 0 = low priority bit 0 ccp2ip : ccp2 interrupt priority bit 1 = high priority 0 = low priority legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown
? 2001 microchip technology inc. advance information ds39541a-page 101 PIC18C601/801 8.1.6 int interrupts external interrupts on the rb0/int0, rb1/int1 and rb2/int2 pins are edge triggered: either rising, if the corresponding intedgx bit is set in the intcon2 reg- ister, or falling, if the intedgx bit is clear. when a valid edge appears on the rbx/intx pin, the corresponding flag bit intxif is set. this interrupt can be disabled by clearing the corresponding enable bit intxie. flag bit intxif must be cleared in software in the interrupt ser- vice routine before re-enabling the interrupt. all exter- nal interrupts (int0, int1 and int2) can wake-up the processor from sleep, if bit intxie was set prior to going into sleep. if the global interrupt enable bit gie is set, the processor will branch to the interrupt vector following wake-up. interrupt priority for int1 and int2 is determined by the value contained in the interrupt priority bits int1ip (intcon3 register) and int2ip (intcon3 register). there is no priority bit associated with int0; it is always a high priority interrupt source. 8.1.7 tmr0 interrupt in 8-bit mode (which is the default), an overflow (0ffh 00h) in the tmr0 register will set flag bit tmr0if. in 16-bit mode, an overflow (0ffffh 0000h) in the tmr0h:tmr0l registers will set flag bit tmr0if. the interrupt can be enabled/disabled by setting/clear- ing enable bit tmr0ie (intcon register). interrupt prior- ity for timer0 is determined by the value contained in the interrupt priority bit tmr0ip (intcon2 register). see section 10.0 for further details on the timer0 module. 8.1.8 portb interrupt-on-change an input change on portb<7:4> sets flag bit rbif (intcon register). the interrupt can be enabled/ disabled by setting/clearing enable bit rbie (intcon register). interrupt priority for portb interrupt-on- change is determined by the value contained in the interrupt priority bit rbip (intcon2 register). 8.2 context saving during interrupts during an interrupt, the return pc value is saved on the stack. additionally, the wreg, status and bsr regis- ters are saved on the fast return stack. if a fast return from interrupt is not used (see section 4.3), the user may need to save the wreg, status and bsr regis- ters in software. depending on the user ? s application, other registers may also need to be saved. example 8-1 saves and restores the wreg, status and bsr registers during an interrupt service routine. example 8-1: saving status, wreg and bsr registers in ram movwf w_temp ; w_temp is in low access bank movff status, status_temp ; status_temp located anywhere movff bsr, bsr_temp ; bsr located anywhere ; ; user isr code ; movff bsr_temp, bsr ; restore bsr movf w_temp, w ; restore wreg movff status_temp, status ; restore status
PIC18C601/801 ds39541a-page 102 advance information ? 2001 microchip technology inc. notes:
? 2001 microchip technology inc. advance information ds39541a-page 103 PIC18C601/801 9.0 i/o ports depending on the device selected, there are up to 9 ports available. some pins of the i/o ports are multi- plexed with an alternate function from the peripheral features on the device. in general, when a peripheral is enabled, that pin may not be used as a general purpose i/o pin. each port has three registers for its operation. these registers are: tris register (data direction register) port register (reads the levels on the pins of the device) lat register (output latch) the data latch (lat register) is useful for read-modify- write operations on the value that the i/o pins are driving. 9.1 porta, trisa and lata registers porta is a 6-bit wide, bi-directional port. the corre- sponding data direction register is trisa. setting a trisa bit (= 1) will make the corresponding porta pin an input (i.e., put the corresponding output driver in a hi-impedance mode). clearing a trisa bit (= 0) will make the corresponding porta pin an output (i.e., put the contents of the output latch on the selected pin). on a power-on reset, these pins are configured as analog inputs and read as '0'. reading the porta register reads the status of the pins, whereas writing to it will write to the port latch. read-modify-write operations on the lata register, reads and writes the latched output value for porta. the ra4 pin is multiplexed with the timer0 module clock input to become the ra4/t0cki pin. the ra4/ t0cki pin is a schmitt trigger input and an open drain output. all other ra port pins have ttl input levels and full cmos output drivers. the other porta pins are multiplexed with analog inputs and the analog v ref + and v ref - inputs. the operation of each pin is selected by clearing/setting the control bits in the adcon1 register (a/d control register1). on a power-on reset, these pins are con- figured as analog inputs and read as '0'. the trisa register controls the direction of the ra pins, even when they are being used as analog inputs. the user must ensure the bits in the trisa register are maintained set when using them as analog inputs. example 9-1: initializing porta figure 9-1: ra3:ra0 and ra5 pins block diagram note: on a power-on reset, porta pins ra3:ra0 and ra5 default to analog inputs. clrf porta ; initialize porta by ; clearing output ; data latches clrf lata ; alternate method ; to clear output ; data latches movlw 07h ; configure a/d movwf adcon1 ; for digital inputs movlw 0cfh ; value used to ; initialize data ; direction movwf trisa ; set ra3:ra0 as inputs ; ra5:ra4 as outputs data bus q d q ck q d q ck qd en p n wr lata wr trisa data latch tris latch rd trisa rd porta v ss v dd i/o pin (1) note 1: i/o pins have diode protection to v dd and v ss . analog input mode ttl input buffer to a/d converter and lvd modules rd lata or wr porta ss input (ra5 only)
PIC18C601/801 ds39541a-page 104 advance information ? 2001 microchip technology inc. figure 9-2: ra4/t0cki pin block diagram table 9-1: porta functions table 9-2: summary of registers associated with porta data bus wr trisa rd porta data latch tris latch rd trisa schmitt trigger input buffer n v ss i/o pin (1) tmr0 clock input note 1: i/o pin has diode protection to v ss only. q d q ck q d q ck en qd en rd lata wr lata or wr porta name bit# buffer function ra0/an0 bit0 ttl input/output or analog input ra1/an1 bit1 ttl input/output or analog input ra2/an2/v ref - bit2 ttl input/output or analog input or v ref - ra3/an3/v ref + bit3 ttl input/output or analog input or v ref + ra4/t0cki bit4 st/od input/output or external clock input for timer0, output is open drain type ra5/ss/ an4/lvdin bit5 ttl input/output or slave select input for synchronous serial port or analog input or low voltage detect input legend: ttl = ttl input, st = schmitt trigger input, od = open drain name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets porta ? ? ra5 ra4 ra3 ra2 ra1 ra0 --0x 0000 --uu uuuu lata ? latch a data output register -xxx xxxx -uuu uuuu trisa ? porta data direction register -111 1111 -111 1111 adcon1 ? ? vcfg1 vcfg0 pcfg3 pcfg2 pcfg1 pcfg0 --00 0000 --uu uuuu legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. shaded cells are not used by porta.
? 2001 microchip technology inc. advance information ds39541a-page 105 PIC18C601/801 9.2 portb, trisb and latb registers portb is an 8-bit wide, bi-directional port. the corre- sponding data direction register is trisb. setting a trisb bit (= 1) will make the corresponding portb pin an input (i.e., put the corresponding output driver in a hi-impedance mode). clearing a trisb bit (= 0) will make the corresponding portb pin an output ( i.e., put the contents of the output latch on the selected pin). read-modify-write operations on the latb register read and write the latched output value for portb. example 9-2: initializing portb figure 9-3: rb7:rb4 pins block diagram each of the portb pins has a weak internal pull-up. a single control bit can turn on all the pull-ups. this is per- formed by clearing bit rbpu (intcon2 register). the weak pull-up is automatically turned off when the port pin is configured as an output. the pull-ups are disabled on a power-on reset. pin rb3 is multiplexed with the ccp input/output. the weak pull-up for rb3 is disabled when the rb3 pin is configured as ccp pin. by disabling the weak pull-up when pin is configured as ccp, allows the remaining weak pull-up devices of portb to be used while the ccp is being used. four of portb ? s pins, rb7:rb4, have an interrupt-on- change feature. only pins configured as inputs can cause this interrupt to occur (i.e., any rb7:rb4 pin configured as an output is excluded from the interrupt- on-change comparison). the input pins (of rb7:rb4) are compared with the old value latched on the last read of portb. the ? mismatch ? outputs of rb7:rb4 are or ? d together to generate the rb port change interrupt with flag bit rbif (intcon register). this interrupt can wake the device from sleep. the user, in the interrupt service routine, can clear the interrupt in the following manner: a) any read or write of portb (except with the movff instruction). this will end the mismatch condition. b) clear flag bit rbif. a mismatch condition will continue to set flag bit rbif. reading portb will end the mismatch condition and allow flag bit rbif to be cleared. the interrupt-on-change feature is recommended for wake-up on key depression operation and operations where portb is only used for the interrupt-on-change feature. polling of portb is not recommended while using the interrupt-on-change feature. clrf portb ; initialize portb by ; clearing output ; data latches clrf latb ; alternate method ; to clear output ; data latches movlw 0cfh ; value used to ; initialize data ; direction movwf trisb ; set rb3:rb0 as inputs ; rb5:rb4 as outputs ; rb7:rb6 as inputs data latch from other rbpu (2) p v dd i/o pin (1) q d ck q d ck qd en qd en data bus wr latb wr trisb set rbif tris latch rd trisb rd portb rb7:rb4 pins weak pull-up rd portb latch ttl input buffer st buffer rbx/intx q3 q1 rd latb or wr portb note 1: i/o pins have diode protection to v dd and v ss . 2: to enable weak pull-ups, set the appropriate tris bit(s) and clear the rbpu bit (intcon2 register).
PIC18C601/801 ds39541a-page 106 advance information ? 2001 microchip technology inc. figure 9-4: rb2:rb0 pins block diagram figure 9-5: rb3 pin block diagram data latch rbpu (2) p v dd q d ck q d ck qd en data bus wr port wr tris rd tris rd port weak pull-up rd port rbx/intx i/o pin (1) ttl input buffer schmitt trigger buffer tris latch note 1: i/o pins have diode protection to v dd and v ss . 2: to enable weak pull-ups, set the appropriate tris bit(s) and clear the rbpu bit (intcon2 register). data latch p v dd q d ck q d en data bus wr latb or wr trisb rd trisb rd portb weak pull-up ccp2 input ttl input buffer schmitt trigger buffer tris latch rd latb wr portb rbpu (2) ck d enable ccp output rd portb ccp output 1 0 p n v dd v ss i/o pin (1) q q ccp e nable note 1: i/o pin has diode protection to v dd and v ss . 2: to enable weak pull-ups, set the appropriate tris bit(s) and clear the rbpu bit (intcon2<7>).
? 2001 microchip technology inc. advance information ds39541a-page 107 PIC18C601/801 table 9-3: portb functions table 9-4: summary of registers associated with portb name bit# buffer function rb0/int0 bit0 ttl/st (1) input/output pin or external interrupt 0 input. internal software programmable weak pull-up. rb1/int1 bit1 ttl/st (1) input/output pin or external interrupt 1 input. internal software programmable weak pull-up. rb2/int2 bit2 ttl/st (1) input/output pin or external interrupt 2 input. internal software programmable weak pull-up. rb3/ccp2 bit3 ttl/st (3) input/output pin or capture2 input or capture2 output or pwm2 output. internal software programmable weak pull-up. rb4 bit4 ttl input/output pin (with interrupt-on-change). internal software programmable weak pull-up. rb5 bit5 ttl input/output pin (with interrupt-on-change). internal software programmable weak pull-up. rb6 bit6 ttl/st (2) input/output pin (with interrupt-on-change). internal software programmable weak pull-up. serial programming clock. rb7 bit7 ttl/st (2) input/output pin (with interrupt-on-change). internal software programmable weak pull-up. serial programming data. legend: ttl = ttl input, st = schmitt trigger input note 1: this pin is a schmitt trigger input when configured as the external interrupt. 2: this pin is a schmitt trigger input when used in serial programming mode. 3: this pin is a schmitt trigger input when used in a capture input. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets portb rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0 xxxx xxxx uuuu uuuu latb latb data output register xxxx xxxx uuuu uuuu trisb portb data direction register 1111 1111 1111 1111 intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 0000 000x 0000 000u intcon2 rbpu intedg0 intedg1 intedg2 intedg3 tmr0ip ? rbip 1111 1111 1111 1111 intcon3 int2ip int1ip ? int2ie int1ie ? int2if int1if 1100 0000 1100 0000 legend: x = unknown, u = unchanged. shaded cells are not used by portd.
PIC18C601/801 ds39541a-page 108 advance information ? 2001 microchip technology inc. 9.3 portc, trisc and latc registers portc is an 8-bit wide, bi-directional port. the corre- sponding data direction register is trisc. setting a trisc bit (= 1) will make the corresponding portc pin an input (i.e., put the corresponding output driver in a hi-impedance mode). clearing a trisc bit (= 0) will make the corresponding portc pin an output (i.e., put the contents of the output latch on the selected pin). read-modify-write operations on the latc register, read and write the latched output value for portc. portc is multiplexed with several peripheral functions (table 9-5). portc pins have schmitt trigger input buffers. when enabling peripheral functions, care should be taken in defining tris bits for each portc pin. some peripherals override the tris bit to make a pin an out- put, while other peripherals override the tris bit to make a pin an input. the user should refer to the correspond- ing peripheral section for the correct tris bit settings. the pin override value is not loaded into the tris reg- ister. this allows read-modify-write of the tris register, without concern due to peripheral overrides. example 9-3: initializing portc figure 9-6: portc block diagram (peripheral output override) clrf portc ; initialize portc by ; clearing output ; data latches clrf latc ; alternate method ; to clear output ; data latches movlw 0cfh ; value used to ; initialize data ; direction movwf trisc ; set rc3:rc0 as inputs ; rc5:rc4 as outputs ; rc7:rc6 as inputs peripheral out select data bus wr latc wr trisc data latch tris latch rd trisc q d q ck qd en peripheral data out 0 1 q d q ck p n v dd v ss rd portc peripheral data in i/o pin (1) or wr portc rd latc schmitt trigger note 1: i/o pins have diode protection to v dd and v ss . tris override peripheral enable tris override pin override peripheral rc0 yes timer1 osc for timer1/timer3 rc1 yes timer1 osc for timer1/timer3 rc2 no ? rc3 yes spi/i 2 c master clock rc4 yes i 2 c data out rc5 yes spi data out rc6 yes usart async xmit, sync clock rc7 yes usart sync data out
? 2001 microchip technology inc. advance information ds39541a-page 109 PIC18C601/801 table 9-5: portc functions table 9-6: summary of registers associated with portc name bit# buffer type function rc0/t1oso/t13cki bit0 st input/output port pin or timer1 oscillator output or timer1/timer3 clock input. rc1/t1osi bit1 st input/output port pin, timer1 oscillator input. rc2/ccp1 bit2 st input/output port pin or capture1 input/compare1 output/ pwm1 output. rc3/sck/scl bit3 st input/output port pin or synchronous serial clock for spi/i 2 c. rc4/sdi/sda bit4 st input/output port pin or spi data in (spi mode) or data i/o (i 2 c mode). rc5/sdo bit5 st input/output port pin or synchronous serial port data output. rc6/tx/ck bit6 st input/output port pin, addressable usart asynchronous transmit, or addressable usart synchronous clock. rc7/rx/dt bit7 st input/output port pin, addressable usart asynchronous receive, or addressable usart synchronous data. legend: st = schmitt trigger input name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets portc rc7 rc6 rc5 rc4 rc3 rc2 rc1 rc0 xxxx xxxx uuuu uuuu latc latc data output register xxxx xxxx uuuu uuuu trisc portc data direction register 1111 1111 1111 1111 legend: x = unknown, u = unchanged
PIC18C601/801 ds39541a-page 110 advance information ? 2001 microchip technology inc. 9.4 portd, trisd and latd registers portd is an 8-bit wide, bi-directional port. the corre- sponding data direction register is trisd. setting a trisd bit (= 1) will make the corresponding portd pin an input (i.e., put the corresponding output driver in a hi-impedance mode). clearing a trisd bit (= 0) will make the corresponding portd pin an output (i.e., put the contents of the output latch on the selected pin). read-modify-write operations on the latd register reads and writes the latched output value for portd. portd is an 8-bit port with schmitt trigger input buff- ers. each pin is individually configurable as an input or output. portd is multiplexed with the system bus and is avail- able only when the system bus is disabled, by setting ebids bit in register memcon. when operating as the system bus, portd is the low order byte of the address/data bus (ad7:ad0), or as the low order address byte (a15:a8) if the address and data buses are de-multiplexed. example 9-4: initializing portd figure 9-7: portd block diagram in i/o mode note: on a power-on reset, portd defaults to the system bus. clrf portd ; initialize portd by ; clearing output ; data latches clrf latd ; alternate method ; to clear output ; data latches movlw 0cfh ; value used to ; initialize data ; direction movwf trisd ; set rd3:rd0 as inputs ; rd5:rd4 as outputs ; rd7:rd6 as inputs data bus wr latd wr trisd rd portd data latch tris latch rd trisd schmitt trigger input buffer i/o pin q d ck q d ck en qd en rd latd or wr portd note: i/o pins have diode protection to v dd and v ss .
? 2001 microchip technology inc. advance information ds39541a-page 111 PIC18C601/801 figure 9-8: portd block diagram in system bus mode instruction register bus enable data/tris out drive bus system bus control data bus wr latd wr trisd rd portd data latch tris latch rd trisd ttl input buffer i/o pin (1) q d ck q d ck en qd en rd latd or portd 0 1 port data instruction read note 1: i/o pins have protection diodes to v dd and v ss .
PIC18C601/801 ds39541a-page 112 advance information ? 2001 microchip technology inc. table 9-7: portd functions table 9-8: summary of registers associated with portd name bit# buffer type function rd0/ad0/a0 (2) bit0 st/ttl (1) input/output port pin or system bus bit 0 rd1/ad1/a1 (2) bit1 st/ttl (1) input/output port pin or system bus bit 1 rd2/ad2/a2 (2) bit2 st/ttl (1) input/output port pin or system bus bit 2 rd3/ad3/a3 (2) bit3 st/ttl (1) input/output port pin or system bus bit 3 rd4/ad4/a4 (3) bit4 st/ttl (1) input/output port pin or system bus bit 4 rd5/ad5/a5 (2) bit5 st/ttl (1) input/output port pin or system bus bit 5 rd6/ad6/a6 (2) bit6 st/ttl (1) input/output port pin or system bus bit 6 rd7/ad7/a7 (2) bit7 st/ttl (1) input/output port pin or system bus bit 7 legend: st = schmitt trigger input, ttl = ttl input note 1: input buffers are schmitt triggers when in i/o mode and ttl buffers when in system bus mode. 2: rdx is used as a multiplexed address/data bus for PIC18C601 and pic18c801 in 16-bit mode, and as an address only for pic18c801 in 8-bit mode. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets portd rd7 rd6 rd5 rd4 rd3 rd2 rd1 rd0 xxxx xxxx uuuu uuuu latd latd data output register xxxx xxxx uuuu uuuu trisd portd data direction register 1111 1111 1111 1111 memcon ebdis pgrm wait1 wait0 ? ? wm1 wm0 0000 --00 0000 --00 legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. shaded cells are not used by portd.
? 2001 microchip technology inc. advance information ds39541a-page 113 PIC18C601/801 9.5 porte, trise and late registers porte is an 8-bit wide, bi-directional port. the corre- sponding data direction register is trise. setting a trise bit (= 1) will make the corresponding porte pin an input (i.e., put the corresponding output driver in a hi-impedance mode). clearing a trise bit (= 0) will make the corresponding porte pin an output (i.e., put the contents of the output latch on the selected pin). read-modify-write operations on the late register reads and writes the latched output value for porte. porte is an 8-bit port with schmitt trigger input buff- ers. each pin is individually configurable as an input or output. porte is multiplexed with several peripheral functions (table 9-9). porte is multiplexed with the system bus and is avail- able only when the system bus is disabled, by setting ebdis bit in register memcon. when operating as the system bus, porte is configured as the high order byte of the address/data bus (ad15:ad8), or as the high order address byte (a15:a8), if address and data buses are de-multiplexed. example 9-5: initializing porte figure 9-9: porte block diagram in i/o mode note: on power-on reset, porte defaults to the system bus. clrf porte ; initialize porte by ; clearing output ; data latches clrf late ; alternate method ; to clear output ; data latches movlw 03h ; value used to ; initialize data ; direction movwf trise ; set re1:re0 as inputs ; re7:re2 as outputs peripheral out select data bus wr late wr trise data latch tris latch rd trise q d q ck qd en peripheral data out 0 1 q d q ck p n v dd v ss rd porte peripheral data in i/o pin (1) or wr porte rd late schmitt trigger note 1: i/o pins have diode protection to v dd and v ss . tris override peripheral enable tris override pin override peripheral re0 yes external bus re1 yes external bus re2 yes external bus re3 yes external bus re4 yes external bus re5 yes external bus re6 yes external bus re7 yes external bus
PIC18C601/801 ds39541a-page 114 advance information ? 2001 microchip technology inc. figure 9-10: porte block diagram in system bus mode to instruction register external enable data/address out drive system system bus control data bus wr late wr trise rd porte data latch tris latch rd trise ttl input buffer i/o pin (1) q d ck q d ck en qd en rd latd or porte 0 1 port data instruction read note 1: i/o pins have diode protection to v dd and v ss .
? 2001 microchip technology inc. advance information ds39541a-page 115 PIC18C601/801 table 9-9: porte functions table 9-10: summary of registers associated with porte name bit# buffer type function re0/ad8/a8 (2) bit0 st/ttl (1) input/output port pin or address/data bit 8 re1/ad9/a9 (2) bit1 st/ttl (1) input/output port pin or address/data bit 9 re2/ad10/a10 (2) bit2 st/ttl (1) input/output port pin or address/data bit 10 re3/ad11/a11 (2) bit3 st/ttl (1) input/output port pin or address/data bit 11 re4/ad12/a12 (2) bit4 st/ttl (1) input/output port pin or address/data bit 12 re5/ad13/a13 (2) bit5 st/ttl (1) input/output port pin or address/data bit 13 re6/ad14/a14 (2) bit6 st/ttl (1) input/output port pin or address/data bit 14 re7/ad15/a15 (2) bit7 st/ttl (1) input/output port pin or address/data bit 15 legend: st = schmitt trigger input, ttl = ttl input note 1: input buffers are schmitt triggers when in i/o mode and ttl buffers when in system bus mode. 2: rex is used as a multiplexed address/data bus for PIC18C601 and pic18c801 in 16-bit mode, and as an address only for pic18c801 in 8-bit mode. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets trise porte data direction control register 1111 1111 1111 1111 porte read porte pin/write porte data latch xxxx xxxx uuuu uuuu late read porte data latch/write porte data latch xxxx xxxx uuuu uuuu memcon ebdis pgrm wait1 wait0 ? ? wm1 wm0 0000 --00 0000 --00 legend: x = unknown, u = unchanged. shaded cells are not used by porte.
PIC18C601/801 ds39541a-page 116 advance information ? 2001 microchip technology inc. 9.6 portf, latf, and trisf registers portf is an 8-bit wide, bi-directional port. the corre- sponding data direction register is trisf. setting a trisf bit (= 1) will make the corresponding portf pin an input (i.e., put the corresponding output driver in a hi-impedance mode). clearing a trisf bit (= 0) will make the corresponding portf pin an output (i.e., put the contents of the output latch on the selected pin). read-modify-write operations on the latf register reads and writes the latched output value for portf. portf pins, rf2:rf0, are multiplexed with analog inputs. the operation of these pins are selected by adcon0 and adcon1 registers. portf pins, rf3 and rf5, are multiplexed with two of the integrated chip select signals csio and cs1 . for pic18c801, pin rf4 is multiplexed with chip select sig- nal cs2 , while for PIC18C601, it is multiplexed with system bus signal a16. for pic18c801 devices, both csel2 and cselio registers must set to all zero, to enable these pins as i/o pins, while for PIC18C601 devices, only cselio register needs to be set to zero. for PIC18C601 devices, pin rf4 can only be config- ured as i/o when the ebdis bit is set and execution is taking place in internal boot ram. portf pins, rf7:rf6, are multiplexed with the sys- tem bus control signal ub and lb , respectively, when a device with 16-bit bus execution is used. these pins can be configured as i/o pins by setting wm bits in the memcon register to any value other than ? 01 ? . example 9-6: initializing portf example 9-7: programming chip select signals figure 9-11: rf2:rf0 pins block diagram note 1: on power-on reset, portf pins rf2:rf0 default to a/d inputs. 2: on power-on reset, portf pins rf7:rf3 for pic18c801 and pins rf7:rf5, rf3 for PIC18C601, default to system bus signals. clrf portf ; initialize portf by ; clearing output ; data latches clrf latf ; alternate method ; to clear output ; data latches movlw 0fh ; movwf adcon1 ; set portf as digital i/o movlw 0cfh ; value used to ; initialize data ; direction movwf trisf ; set rf3:rf0 as inputs ; rf5:rf4 as outputs ; rf7:rf6 as inputs ? ? ; program chip select to activate cs1 ; for all address less than 03ffffh, ; while activate cs2 for rests of the ; addresses ; csel2 register is secured register. ; before it can be modified it, ; combination lock must be opened movlw 20h ; preload wreg with ; correct csel2 valu bcf intcon, gie ; disable interrupts call unlock ; now unlock it ; lock is open. modify csel2... movwf csel2 ; lock is closed bsf intcon, gie ; re-enable interrupts ; chip select is programmed. ? ? unlock bsf pspcon, cmlk1 bsf pspcon, cmlk0 return ? ? data bus q d q ck q d q ck p n wr latf wr trisf data latch tris latch rd trisf rd portf v ss v dd i/o pin analog input mode st input buffer to a/d converter rd latf or wr portf note: i/o pins have diode protection to v dd and v ss . qd en
? 2001 microchip technology inc. advance information ds39541a-page 117 PIC18C601/801 figure 9-12: rf5:rf3 pins block diagram figure 9-13: rf7:rf6 pins block diagram external enable cs out drive system system bus control data bus wr latf wr trisf rd portf data latch tris latch rd trisf i/o pin (1) q d ck q d ck en qd en rd latf or portf 0 1 port data note 1: i/o pins have diode protection to v dd and v ss . wm = ? 01 ? ub /lb out drive system system bus control data bus wr latf wr trisf rd portf data latch tris latch rd trisf i/o pin (1) q d ck q d ck en qd en rd latf or portf 0 1 port data note 1: i/o pins have diode protection to v dd and v ss .
PIC18C601/801 ds39541a-page 118 advance information ? 2001 microchip technology inc. table 9-11: portf functions note 1: cs2 is available only on pic18c801. table 9-12: summary of registers associated with portf name bit# buffer type function rf0/an5 bit0 st input/output port pin or analog input rf1/an6 bit1 st input/output port pin or analog input rf2/an7 bit2 st input/output port pin or analog input rf3/csio bit3 st input/output port pin or i/o chip select rf4/a16/cs2 (1) bit4 st input/output port pin or chip select 2 or address bit 16 rf5/cs1 bit5 st input/output port pin or chip select 1 rf6/lb bit6 st input/output port pin or low byte select signal for external memory rf7/ub bit7 st input/output port pin or high byte select signal for external memory legend: st = schmitt trigger input name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets trisf portf data direction control register 1111 1111 1111 1111 portf read portf pin/write portf data latch xxxx xxxx uuuu uuuu latf read portf data latch/write portf data latch 0000 0000 uuuu uuuu adcon1 ? ? vcfg1 vcfg0 pcfg3 pcfg2 pcfg1 pcfg0 --00 0000 --00 0000 memcon ebdis pgrm wait1 wait0 ? ? wm1 wm0 0000 --00 0000 --00 legend: x = unknown, u = unchanged. shaded cells are not used by portf.
? 2001 microchip technology inc. advance information ds39541a-page 119 PIC18C601/801 9.7 portg, latg, and trisg registers portg is a 5-bit wide, bi-directional port. the corre- sponding data direction register is trisg. setting a trisg bit (= 1) will make the corresponding portg pin an input (i.e., put the corresponding output driver in a hi-impedance mode). clearing a trisg bit (= 0) will make the corresponding portg pin an output (i.e., put the contents of the output latch on the selected pin). read-modify-write operations on the latg register read and write the latched output value for portg. portg is multiplexed with system bus control signals ale, oe , wrh , wrl and ba0. the wrh signal is the only signal that is disabled and configured as a port pin (rg3) during external program execution in 8-bit mode. all other pins are by default, system bus control sig- nals. portg can be configured as an i/o port by set- ting ebdis bit in the memcon register and when execution is taking place in internal program ram. example 9-8: initializing portg figure 9-14: portg block diagram in i/o mode note: on power-on reset, portg defaults to system bus signals. clrf portg ; initialize portg by ; clearing output ; data latches clrf latg ; alternate method ; to clear output ; data latches movlw 04h ; value used to ; initialize data ; direction movwf trisg ; set rg1:rg0 as outputs ; rg2 as input ; rg4:rg3 as outputs data bus wr latg wr trisg rd portg data latch tris latch rd trisg schmitt trigger input buffer i/o pin (1) q d ck q d ck en qd en rd latg or portg note 1: i/o pins have diode protection to v dd and v ss .
PIC18C601/801 ds39541a-page 120 advance information ? 2001 microchip technology inc. figure 9-15: portg block diagram in system bus mode table 9-13: portg functions table 9-14: summary of registers associated with portg external enable control out drive system system bus control data bus wr latg wr trisg rd portg data latch tris latch rd trisg i/o pin (1) q d ck q d ck en qd en rd latg or portg 0 1 port data note 1: i/o pins have diode protection to v dd and v ss . name bit# buffer type function rg0/ale bit0 st input/output port pin or address latch enable signal for external memory rg1/oe bit1 st input/output port pin or output enable signal for external memory rg2/wrl bit2 st input/output port pin or write low byte signal for external memory rg3/wrh bit3 st input/output port pin or write high byte signal for external memory rg4/ba0 bit4 st input/output port pin or byte address 0 signal for external memory legend: st = schmitt trigger input name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets trisg portg data direction control register ---1 1111 ---1 1111 portg read portg pin/write portg data latch ---x xxxx ---u uuuu latg read portg data latch/write portg data latch ---x xxxx ---u uuuu memcon ebdis pgrm wait1 wait0 ? ? wm1 wm0 0000 --00 0000 --00 legend: x = unknown, u = unchanged. shaded cells are not used by portg.
? 2001 microchip technology inc. advance information ds39541a-page 121 PIC18C601/801 9.8 porth, lath, and trish registers porth is an 8-bit wide, bi-directional i/o port. the cor- responding data direction register is trish. setting a trish bit (= 1) will make the corresponding porth pin an input (i.e., put the corresponding output driver in a hi-impedance mode). clearing a trish bit (= 0) will make the corresponding porth pin an output (i.e., put the contents of the output latch on the selected pin). read-modify-write operations on the lath register read and write the latched output value for porth. pins rh7:rh4 are multiplexed with analog inputs an18:an11, while pins rh3:rh0 are multiplexed with system address bus a19:a16. by default, pins rh7:rh4 will setup as a/d inputs and pins rh3:rh0 will setup as system address bus. register adcon1 configures rh7:rh4 as i/o or a/d inputs. register memcon configures rh3:rh0 as i/o or system bus pins. example 9-9: initializing porth figure 9-16: rh3:rh0 pins block diagram in i/o mode figure 9-17: rh7:rh4 pins block diagram note: porth is available only on pic18c801 devices. note 1: on power-on reset, porth pins rh7:rh4 default to a/d inputs and read as ? 0 ? . 2: on power-on reset, porth pins rh3:rh0 default to system bus signals. clrf porth ; initialize porth by ; clearing output ; data latches clrf lath ; alternate method ; to clear output ; data latches movlw 0fh ; movwf adcon1 ; movlw 0cfh ; value used to ; initialize data ; direction movwf trish ; set rh3:rh0 as inputs ; rh5:rh4 as outputs ; rh7:rh6 as inputs data bus wr lath wr trish rd porth data latch tris latch rd trish schmitt trigger input buffer i/o pin (1) q d ck q d ck en qd en rd lath or porth note 1: i/o pins have diode protection to v dd and v ss . data bus wr lath wr trish rd porth data latch tris latch rd trish schmitt trigger input buffer i/o pin (1) q d ck q d ck en qd en rd lath or porth to a/d converter note 1: i/o pins have diode protection to v dd and v ss .
PIC18C601/801 ds39541a-page 122 advance information ? 2001 microchip technology inc. figure 9-18: rh3:rh0 pins block diagram in system bus mode to instruction register external enable. address out drive system system bus control data bus wr lath wr trish rd porth data latch tris latch rd trish ttl input buffer i/o pin (1) q d ck q d ck en qd en rd latd or porth 0 1 port data instruction read note 1: i/o pins have diode protection to v dd and v ss .
? 2001 microchip technology inc. advance information ds39541a-page 123 PIC18C601/801 table 9-15: porth functions table 9-16: summary of registers associated with porth name bit# buffer type function rh0/a16 (1) bit0 st input/output port pin or address bit 16 for external memory interface rh1/a17 (1) bit1 st input/output port pin or address bit 17 for external memory interface rh2/a18 (1) bit2 st input/output port pin or address bit 18 for external memory interface rh3/a19 (1) bit3 st input/output port pin or address bit 19 for external memory interface rh4/an8 (1) bit4 st input/output port pin or analog input channel 8 rh5/an9 (1) bit5 st input/output port pin or analog input channel 9 rh6/an10 (1) bit6 st input/output port pin or analog input channel 10 rh7/an11 (1) bit7 st input/output port pin or analog input channel 11 legend: st = schmitt trigger input note 1: porth is available only on pic18c801 devices. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets trish porth data direction control register 1111 1111 1111 1111 porth read porth pin/write porth data latch xxxx xxxx uuuu uuuu lath read porth data latch/write porth data latch xxxx xxxx uuuu uuuu adcon1 ? ? vcfg1 vcfg0 pcfg3 pcfg2 pcfg1 pcfg0 --00 0000 --00 0000 memcon ebdis pgrm wait1 wait0 ? ? wm1 wm0 0000 --00 0000 --00 legend: x = unknown, u = unchanged, - = unimplemented. shaded cells are not used by porth.
PIC18C601/801 ds39541a-page 124 advance information ? 2001 microchip technology inc. 9.9 portj, latj, and trisj registers portj is an 8-bit wide, bi-directional i/o port. the cor- responding data direction register is trisj. setting a trisj bit (= 1) will make the corresponding portj pin an input (i.e., put the corresponding output driver in a hi-impedance mode). clearing a trisj bit (= 0) will make the corresponding portj pin an output (i.e., put the contents of the output latch on the selected pin). read-modify-write operations on the latj register read and write the latched output value for portj. portj is multiplexed with de-multiplexed system data bus d7:d0, when device is configured in 8-bit execution mode. register memcon configures portj as i/o or system bus pins. example 9-10: initializing portj figure 9-19: portj block diagram in i/o mode note: portj is available only on pic18c801 devices. note: on power-on reset, portj defaults to system bus signals. clrf portj ; initialize portj by ; clearing output ; data latches clrf latj ; alternate method ; to clear output ; data latches movlw 0cfh ; value used to ; initialize data ; direction movwf trisj ; set rj3:rj0 as inputs ; rj5:rj4 as outputs ; rj7:rj6 as inputs data bus wr latj wr trisj rd portj data latch tris latch rd trisj schmitt trigger input buffer i/o pin (1) q d ck q d ck en qd en rd latj or portj note 1: i/o pins have diode protection to v dd and v ss .
? 2001 microchip technology inc. advance information ds39541a-page 125 PIC18C601/801 figure 9-20: portj block diagram in system data bus mode to instruction register external enable data out drive system system bus control data bus wr latj wr trisj rd portj data latch tris latch rd trisj ttl input buffer i/o pin (1) q d ck q d ck en qd en rd latd or portj 0 1 port data instruction read sr note 1: i/o pins have diode protection to v dd and v ss .
PIC18C601/801 ds39541a-page 126 advance information ? 2001 microchip technology inc. table 9-17: portj functions table 9-18: summary of registers associated with portj name bit# buffer type function rj0/d0 (1) bit0 st/ttl input/output port pin or data bit 0 for external memory interface rj1/d1 (1) bit1 st/ttl input/output port pin or data bit 1 for external memory interface rj2/d2 (1) bit2 st/ttl input/output port pin or data bit 2 for external memory interface rj3/d3 (1) bit3 st/ttl input/output port pin or data bit 3 for external memory interface rj4/d4 (1) bit4 st/ttl input/output port pin or data bit 4 for external memory interface rj5/d5 (1) bit5 st/ttl input/output port pin or data bit 5 for external memory interface rj6/d6 (1) bit6 st/ttl input/output port pin or data bit 6 for external memory interface rj7/d7 (1) bit7 st/ttl input/output port pin or data bit 7 for external memory interface legend: st = schmitt trigger input, ttl = ttl input note 1: portj is available only on pic18c801 devices. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets trisj portj data direction control register 1111 1111 1111 1111 portj read portj pin/write portj data latch xxxx xxxx uuuu uuuu latj read portj data latch/write portj data latch xxxx xxxx uuuu uuuu memcon ebdis pgrm wait1 wait0 ? ? wm1 wm0 0000 --00 0000 --00 legend: x = unknown, u = unchanged. shaded cells are not used by portj.
? 2001 microchip technology inc. advance information ds39541a-page 127 PIC18C601/801 10.0 timer0 module the timer0 module has the following features: software selectable as an 8-bit or 16-bit timer/ counter readable and writable dedicated 8-bit software programmable prescaler clock source selectable to be external or internal interrupt on overflow from ffh to 00h in 8-bit mode and ffffh to 0000h in 16-bit mode edge select for external clock register 10-1 shows the timer0 control register (t0con). figure 10-1 shows a simplified block diagram of the timer0 module in 8-bit mode and figure 10-2 shows a simplified block diagram of the timer0 module in 16-bit mode. the t0con register is a readable and writable register that controls all the aspects of timer0, including the prescale selection. register 10-1: t0con register note: timer0 is enabled on por. r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 tmr0on t08bit t0cs t0se psa t0ps2 t0ps1 t0ps0 bit 7 bit 0 bit 7 tmr0on: timer0 on/off control bit 1 = enables timer0 0 = stops timer0 bit 6 t08bit : timer0 8-bit/16-bit control bit 1 = timer0 is configured as an 8-bit timer/counter 0 = timer0 is configured as a 16-bit timer/counter bit 5 t0cs : timer0 clock source select bit 1 = transition on t0cki pin 0 = internal instruction cycle clock (clkout) bit 4 t0se : timer0 source edge select bit 1 = increment on high-to-low transition on t0cki pin 0 = increment on low-to-high transition on t0cki pin bit 3 psa : timer0 prescaler assignment bit 1 = timer0 prescaler is not assigned. timer0 clock input bypasses prescaler. 0 = timer0 prescaler is assigned. timer0 clock input comes from prescaler output. bit 2-0 t0ps2:t0ps0 : timer0 prescaler select bits 111 = 1:256 prescale value 110 = 1:128 prescale value 101 = 1:64 prescale value 100 = 1:32 prescale value 011 = 1:16 prescale value 010 = 1:8 prescale value 001 = 1:4 prescale value 000 = 1:2 prescale value legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown
PIC18C601/801 ds39541a-page 128 advance information ? 2001 microchip technology inc. figure 10-1: timer0 block diagram in 8-bit mode figure 10-2: timer0 block diagram in 16-bit mode note 1: upon reset, timer0 is enabled in 8-bit mode with clock input from t0cki max. prescale. 2: i/o pins have diode protection to v dd and v ss . ra4/t0cki t0se 0 1 0 1 pin (2) t0cs (1) f osc /4 programmable prescaler sync with internal clocks tmr0l (2 t cy delay) data bus 8 psa t0ps2, t0ps1, t0ps0 set interrupt flag bit tmr0if on overflow 3 ra4/t0cki t0se 0 1 0 1 t0cs (1) f osc /4 programmable prescaler sync with internal clocks tmr0l (2 t cy delay) data bus<7:0> 8 psa t0ps2, t0ps1, t0ps0 set interrupt flag bit tmr0if on overflow 3 tmr0 tmr0h high byte 8 8 8 read tmr0l write tmr0l note 1: upon reset, timer0 is enabled in 8-bit mode with clock input from t0cki max. prescale. 2: i/o pins have diode protection to v dd and v ss . pin (2)
? 2001 microchip technology inc. advance information ds39541a-page 129 PIC18C601/801 10.1 timer0 operation timer0 can operate as a timer or as a counter. timer mode is selected by clearing the t0cs bit. in timer mode, the timer0 module will increment every instruction cycle (without prescaler). if the tmr0l reg- ister is written, the increment is inhibited for the follow- ing two instruction cycles. the user can work around this by writing an adjusted value to the tmr0l register. counter mode is selected by setting the t0cs bit. in counter mode, timer0 will increment either on every rising, or falling edge, of pin ra4/t0cki. the incre- menting edge is determined by the timer0 source edge select bit (t0se). clearing the t0se bit selects the rising edge. restrictions on the external clock input are discussed below. when an external clock input is used for timer0, it must meet certain requirements. the requirements ensure the external clock can be synchronized with the internal phase clock (t osc ). also, there is a delay in the actual incrementing of timer0 after synchronization. 10.2 prescaler an 8-bit counter is available as a prescaler for the timer0 module. the prescaler is not readable or writable. the psa and t0ps2:t0ps0 bits determine the prescaler assignment and prescale ratio. clearing bit psa will assign the prescaler to the timer0 module. when the prescaler is assigned to the timer0 module, prescale values of 1:2, 1:4, ..., 1:256 are selectable. when assigned to the timer0 module, all instructions writing to the tmr0 register (e.g. clrf tmr0, movwf tmr0, bsf tmr0, x .... etc.) will clear the prescaler count. 10.2.1 switching prescaler assignment the prescaler assignment is fully under software con- trol (i.e., it can be changed ? on-the-fly ? during program execution). 10.3 timer0 interrupt the tmr0 interrupt is generated when the tmr0 reg- ister overflows from ffh to 00h in 8-bit mode, or ffffh to 0000h in 16-bit mode. this overflow sets the tmr0if bit. the interrupt can be masked by clearing the tmr0ie bit. the tmr0if bit must be cleared in soft- ware by the timer0 module interrupt service routine before re-enabling this interrupt. the tmr0 interrupt cannot awaken the processor from sleep, since the timer is shut-off during sleep. 10.4 16-bit mode timer reads and writes timer0 can be set in 16-bit mode by clearing t0con t08bit. registers tmr0h and tmr0l are used to access 16-bit timer value. tmr0h is not the high byte of the timer/counter in 16-bit mode, but is actually a buffered version of the high byte of timer0 (refer to figure 10-1). the high byte of the timer0 counter/timer is not directly readable nor writable. tmr0h is updated with the contents of the high byte of timer0 during a read of tmr0l. this pro- vides the ability to read all 16-bits of timer0 without having to verify that the read of the high and low byte were valid, due to a rollover between successive reads of the high and low byte. a write to the high byte of timer0 must also take place through the tmr0h buffer register. timer0 high byte is updated with the contents of the buffered value of tmr0h, when a write occurs to tmr0l. this allows all 16-bits of timer0 to be updated at once. table 10-1: registers associated with timer0 note: writing to tmr0 when the prescaler is assigned to timer0, will clear the prescaler count but will not change the prescaler assignment. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets tmr0l timer0 module ? s low byte register xxxx xxxx uuuu uuuu tmr0h timer0 module ? s high byte register 0000 0000 0000 0000 intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 0000 000x 0000 000u t0con tmr0on t08bit t0cs t0se psa t0ps2 t0ps1 t0ps0 1111 1111 1111 1111 trisa ? porta data direction register --11 1111 --11 1111 legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. shaded cells are not used by timer0.
PIC18C601/801 ds39541a-page 130 advance information ? 2001 microchip technology inc. 11.0 timer1 module the timer1 module timer/counter has the following features: 16-bit timer/counter (two 8-bit registers: tmr1h and tmr1l) readable and writable (both registers) internal or external clock select interrupt on overflow from ffffh to 0000h reset from ccp module special event trigger register 11-1 shows the timer1 control register. this register controls the operating mode of the timer1 module as well as contains the timer1 oscillator enable bit (t1oscen). timer1 can be enabled/disabled by setting/clearing control bit tmr1on (t1con register). figure 11-1 is a simplified block diagram of the timer1 module. register 11-1: t1con register note: timer1 is disabled on por. r/w-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rd16 ? t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on bit 7 bit 0 bit 7 rd16: 16-bit read/write mode enable bit 1 = enables register read/write of timer1 in one 16-bit operation 0 = enables register read/write of timer1 in two 8-bit operations bit 6 unimplemented: read as '0' bit 5-4 t1ckps1:t1ckps0 : timer1 input clock prescale select bits 11 = 1:8 prescale value 10 = 1:4 prescale value 01 = 1:2 prescale value 00 = 1:1 prescale value bit 3 t1oscen: timer1 oscillator enable bit 1 = timer1 oscillator is enabled 0 = timer1 oscillator is shut-off the oscillator inverter and feedback resistor are turned off to eliminate power drain. bit 2 t1sync : timer1 external clock input synchronization select bit when tmr1cs = 1: 1 = do not synchronize external clock input 0 = synchronize external clock input when tmr1cs = 0: this bit is ignored. timer1 uses the internal clock when tmr1cs = 0. bit 1 tmr1cs: timer1 clock source select bit 1 = external clock from pin rc0/t1oso/t13cki (on the rising edge) 0 = internal clock (f osc /4) bit 0 tmr1on: timer1 on bit 1 = enables timer1 0 = stops timer1 legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown
? 2001 microchip technology inc. advance information ds39541a-page 131 PIC18C601/801 11.1 timer1 operation timer1 can operate in one of these modes: as a timer as a synchronous counter as an asynchronous counter the operating mode is determined by the clock select bit, tmr1cs (t1con register). when tmr1cs is clear, timer1 increments every instruction cycle. when tmr1cs is set, timer1 incre- ments on every rising edge of the external clock input or the timer1 oscillator, if enabled. when the timer1 oscillator is enabled (t1oscen is set), the rc1/t1osi and rc0/t1oso/t1cki pins become inputs. that is, the trisc<1:0> value is ignored. timer1 also has an internal ? reset input ? . this reset can be generated by the ccp module (table 14.0). figure 11-1: timer1 block diagram note: when timer1 is configured in an asyn- chronous mode, care must be taken to make sure that there is no incoming pulse while timer1 is being turned off. if there is an incoming pulse while timer1 is being turned off, timer1 value may become unpredictable. if an application requires that timer1 be turned off and if it is possible that timer1 may receive an incoming pulse while being turned off, synchronize the external clock first, by clearing the t1sync bit of register t1con. please note that this may cause timer1 to miss up to one count. tmr1h tmr1l t1sync tmr1cs t1ckps1:t1ckps0 sleep input f osc /4 internal clock tmr1on on/off prescaler 1, 2, 4, 8 synchronize det 1 0 0 1 synchronized clock input 2 tmr1if overflow tmr1 clr ccp special event trigger t1oscen enable oscillator (1) t1osc interrupt flag bit note 1: when enable bit t1oscen is cleared, the inverter and feedback resistor are turned off. this reduces power drain. t1osi t13cki/t1oso
PIC18C601/801 ds39541a-page 132 advance information ? 2001 microchip technology inc. figure 11-2: timer1 block diagram: 16-bit read/write mode timer 1 tmr1l t1osc t1sync tmr1cs t1ckps1:t1ckps0 sleep input t1oscen enable oscillator (1) tmr1if overflow interrupt f osc /4 internal clock tmr1on on/off prescaler 1, 2, 4, 8 synchronize det 1 0 0 1 synchronized clock input 2 t13cki/t1oso t1osi tmr1 flag bit note 1: when enable bit t1oscen is cleared, the inverter and feedback resistor are turned off. this reduces power drain. high byte data bus<7:0> 8 tmr1h 8 8 8 read tmr1l write tmr1l special event trigger
? 2001 microchip technology inc. advance information ds39541a-page 133 PIC18C601/801 11.2 timer1 oscillator a crystal oscillator circuit is built-in between pins t1osi (input) and t1oso (amplifier output). it is enabled by setting control bit t1oscen (t1con register). the oscillator is a low power oscillator rated up to 200 khz. it will continue to run during sleep. it is primarily intended for a 32 khz crystal. table 11-1 shows the capacitor selection for the timer1 oscillator. the user must provide a software time delay to ensure proper start-up of the timer1 oscillator. table 11-1: capacitor selection for the alternate oscillator 11.3 timer1 interrupt the tmr1 register pair (tmr1h:tmr1l) increments from 0000h to ffffh and rolls over to 0000h. the tmr1 interrupt, if enabled, is generated on overflow, which is latched in interrupt flag bit tmr1if (pir regis- ters). this interrupt can be enabled/disabled by setting/ clearing tmr1 interrupt enable bit tmr1ie (pie registers). 11.4 resetting timer1 using a ccp trigger output if the ccp module is configured in compare mode to generate a ? special event trigger" (ccp1m3:ccp1m0 = 1011 ), this signal will reset timer1 and start an a/d conversion (if the a/d module is enabled). timer1 must be configured for either timer, or synchro- nized counter mode, to take advantage of this feature. if timer1 is running in asynchronous counter mode, this reset operation may not work. in the event that a write to timer1 coincides with a special event trigger from ccp1, the write will take precedence. in this mode of operation, the ccpr1h:ccpr1l regis- ters pair, effectively becomes the period register for timer1. 11.5 timer1 16-bit read/write mode timer1 can be configured for 16-bit reads and writes (see figure 11-2). when the rd16 control bit (t1con registe r ) is set, the address for tmr1h is mapped to a buffer register for the high byte of timer1. a read from tmr1l will load the contents of the high byte of timer1 into the timer1 high byte buffer. this provides the user with the ability to accurately read all 16 bits of timer1, without having to determine whether a read of the high byte followed by a read of the low byte is valid, due to a rollover between reads. a write to the high byte of timer1 must also take place through the tmr1h buffer register. timer1 high byte is updated with the contents of tmr1h when a write occurs to tmr1l. this allows a user to write all 16-bits to both the high and low bytes of timer1 at once. the high byte of timer1 is not directly readable or writ- able in this mode. all reads and writes must take place through the timer1 high byte buffer register. writes to tmr1h do not clear the timer1 prescaler. the prescaler is only cleared on writes to tmr1l. osc type freq c1 c2 lp 32 khz tbd (1) tbd (1) crystal to be tested: 32.768 khz epson c-001r32.768k-a 20 ppm note 1: microchip suggests 33 pf as a starting point in validating the oscillator circuit. 2: higher capacitance increases the stability of the oscillator, but also increases the start-up time. 3: since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appro- priate values of external components. 4: capacitor values are for design guidance only. note: the special event triggers from the ccp1 module will not set interrupt flag bit tmr1if (pir registers).
PIC18C601/801 ds39541a-page 134 advance information ? 2001 microchip technology inc. table 11-2: registers associated with timer1 as a timer/counter name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets intcon gie/ gieh peie/ giel tmr0ie int0ie rbie tmr0if int0if rbif 0000 000x 0000 000u pir1 ? adif rcif txif sspif ccp1if tmr2if tmr1if -000 0000 -000 0000 pie1 ? adie rcie txie sspie ccp1ie tmr2ie tmr1ie -000 0000 -000 0000 ipr1 ? adip rcip txip sspip ccp1ip tmr2ip tmr1ip -000 0000 -000 0000 tmr1l holding register for the least significant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu tmr1h holding register for the most significant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu t1con rd16 ? t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on 0-00 0000 u-uu uuuu legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. shaded cells are not used by the timer1 module.
? 2001 microchip technology inc. advance information ds39541a-page 135 PIC18C601/801 12.0 timer2 module the timer2 module timer has the following features: 8-bit timer (tmr2 register) 8-bit period register (pr2) readable and writable (both registers) software programmable prescaler (1:1, 1:4, 1:16) software programmable postscaler (1:1 to 1:16) interrupt on tmr2 match of pr2 ssp module optional use of tmr2 output to generate clock shift register 12-1 shows the timer2 control register. timer2 can be shut-off by clearing control bit tmr2on (t2con register), to minimize power consumption. figure 12-1 is a simplified block diagram of the timer2 module. the prescaler and postscaler selection of timer2 are controlled by this register. 12.1 timer2 operation timer2 can be used as the pwm time-base for the pwm mode of the ccp module. the tmr2 register is read- able and writable, and is cleared on any device reset. the input clock (f osc /4) has a prescale option of 1:1, 1:4, or 1:16, selected by control bits t2ckps1:t2ckps0 (t2con register). the match out- put of tmr2 goes through a 4-bit postscaler (which gives a 1:1 to 1:16 scaling inclusive) to generate a tmr2 interrupt (latched in flag bit tmr2if, pir registers). the prescaler and postscaler counters are cleared when any of the following occurs: a write to the tmr2 register a write to the t2con register any device reset (power-on reset, mclr reset, or watchdog timer reset) tmr2 is not cleared when t2con is written. register 12-1: t2con register note: timer2 is disabled on por. u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? toutps3 toutps2 toutps1 toutps0 tmr2on t2ckps1 t2ckps0 bit 7 bit 0 bit 7 unimplemented: read as '0' bit 6-3 toutps3:toutps0 : timer2 output postscale select bits 0000 = 1:1 postscale 0001 = 1:2 postscale 1111 = 1:16 postscale bit 2 tmr2on : timer2 on bit 1 = timer2 is on 0 = timer2 is off bit 1-0 t2ckps1:t2ckps0 : timer2 clock prescale select bits 00 = prescaler is 1 01 = prescaler is 4 1x = prescaler is 16 legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown
PIC18C601/801 ds39541a-page 136 advance information ? 2001 microchip technology inc. 12.2 timer2 interrupt the timer2 module has an 8-bit period register, pr2. timer2 increments from 00h until it matches pr2 and then resets to 00h on the next increment cycle. pr2 is a readable and writable register. the pr2 register is initialized to ffh upon reset. 12.3 output of tmr2 the output of tmr2 (before the postscaler) is a clock input to the synchronous serial port module, which optionally uses it to generate the shift clock. figure 12-1: timer2 block diagram table 12-1: registers associated with timer2 as a timer/counter comparator tmr2 sets flag tmr2 output (1) reset postscaler prescaler pr2 2 f osc /4 1:1 1:16 1:1, 1:4, 1:16 eq 4 bit tmr2if note 1: tmr2 register output can be software selected by the ssp module as a baud clock. to toutps3:toutps0 t2ckps1:t2ckps0 name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets intcon gie/ gieh peie/ giel tmr0ie int0ie rbie tmr0if int0if rbif 0000 000x 0000 000u pir1 ? adif rcif txif sspif ccp1if tmr2if tmr1if -000 0000 -000 0000 pie1 ? adie rcie txie sspie ccp1ie tmr2ie tmr1ie -000 0000 -000 0000 ipr1 ? adip rcip txip sspip ccp1ip tmr2ip tmr1ip -000 0000 -000 0000 tmr2 timer2 module ? s register 0000 0000 0000 0000 t2con ? toutps3 toutps2 toutps1 toutps0 tmr2on t2ckps1 t2ckps0 -000 0000 -000 0000 pr2 timer2 period register 1111 1111 1111 1111 legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. shaded cells are not used by the timer2 module.
? 2001 microchip technology inc. advance information ds39541a-page 137 PIC18C601/801 13.0 timer3 module the timer3 module timer/counter has the following features: 16-bit timer/counter (two 8-bit registers: tmr3h and tmr3l) readable and writable (both registers) internal or external clock select interrupt on overflow from ffffh to 0000h reset from ccp module trigger figure 13-1 is a simplified block diagram of the timer3 module. register 13-1 shows the timer3 control register. this register controls the operating mode of the timer3 module and sets the ccp clock source. register 11-1 shows the timer1 control register. this register controls the operating mode of the timer1 module, as well as contains the timer1 oscillator enable bit (t1oscen), which can be a clock source for timer3. register 13-1: t3con register note: timer3 is disabled on por. r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rd16 t3ccp2 t3ckps1 t3ckps0 t3ccp1 t3sync tmr3cs tmr3on bit 7 bit 0 bit 7 rd16: 16-bit read/write mode enable 1 = enables register read/write of timer3 in one 16-bit operation 0 = enables register read/write of timer3 in two 8-bit operations bit 6,3 t3ccp2:t3ccp1: timer3 and timer1 to ccpx enable bits 1x = timer3 is the clock source for compare/capture ccp modules 01 = timer3 is the clock source for compare/capture of ccp2, timer1 is the clock source for compare/capture of ccp1 00 = timer1 is the clock source for compare/capture ccp modules bit 5-4 t3ckps1:t3ckps0 : timer3 input clock prescale select bits 11 = 1:8 prescale value 10 = 1:4 prescale value 01 = 1:2 prescale value 00 = 1:1 prescale value bit 2 t3sync : timer3 external clock input synchronization control bit (not usable if the system clock comes from timer1/timer3) when tmr3cs = 1: 1 = do not synchronize external clock input 0 = synchronize external clock input when tmr3cs = 0: this bit is ignored. timer3 uses the internal clock when tmr3cs = 0. bit 1 tmr3cs: timer3 clock source select bit 1 = external clock input from timer1 oscillator or t1cki (on the rising edge after the first falling edge) 0 = internal clock (f osc /4) bit 0 tmr3on: timer3 on bit 1 = enables timer3 0 = stops timer3 legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown
PIC18C601/801 ds39541a-page 138 advance information ? 2001 microchip technology inc. 13.1 timer3 operation timer3 can operate in one of these modes: as a timer as a synchronous counter as an asynchronous counter the operating mode is determined by the clock select bit, tmr3cs (t3con register). when tmr3cs = 0, timer3 increments every instruc- tion cycle. when tmr3cs = 1, timer3 increments on every rising edge of the timer1 external clock input or the timer1 oscillator, if enabled. when the timer1 oscillator is enabled (t1oscen is set), the rc1/t1osi and rc0/t1oso/t1cki pins become inputs. that is, the trisc<1:0> value is ignored. timer3 also has an internal ? reset input ? . this reset can be generated by the ccp module (section 13.0). figure 13-1: timer3 block diagram figure 13-2: timer3 block diagram configured in 16-bit read/write mode tmr3h tmr3l t1osc t3sync tmr3cs t3ckps1:t3ckps0 sleep input t1oscen enable oscillator (1) tmr3if overflow interrupt f osc /4 internal clock tmr3on on/off prescaler 1, 2, 4, 8 synchronize det 1 0 0 1 synchronized clock input 2 t1oso/ t1osi flag bit (3) note 1: when enable bit t1oscen is cleared, the inverter and feedback resistor are turned off. this reduces power drain. t13cki ccp special trigger t3ccpx clr tmr3l t1osc t3sync tmr3cs t3ckps1:t3ckps0 sleep input t1oscen enable oscillator (1) f osc /4 internal clock tmr3on on/off prescaler 1, 2, 4, 8 synchronize det 1 0 0 1 synchronized clock input 2 t1oso/ t1osi tmr3 t13cki clr ccp special trigger t3ccpx to timer1 clock input note 1: when enable bit t1oscen is cleared, the inverter and feedback resistor are turned off. this reduces power drain. tmr3h data bus<7:0> 8 tmr3h 8 8 8 read tmr3l write tmr3l tmr3if overflow interrupt flag bit
? 2001 microchip technology inc. advance information ds39541a-page 139 PIC18C601/801 13.2 timer1 oscillator the timer1 oscillator may be used as the clock source for timer3. the timer1 oscillator is enabled by setting the t1oscen bit (t1con register). the oscillator is a low power oscillator rated up to 200 khz. refer to ? timer1 module ? , section 11.0, for timer1 oscillator details. 13.3 timer3 interrupt the tmr3 register pair (tmr3h:tmr3l) increments from 0000h to ffffh and rolls over to 0000h. the tmr3 interrupt, if enabled, is generated on overflow, which is latched in interrupt flag bit tmr3if (pie registers). this interrupt can be enabled/disabled by setting/clearing tmr3 interrupt enable bit tmr3ie (pie registers). 13.4 resetting timer3 using a ccp trigger output if the ccp module is configured in compare mode to generate a ? special event trigger" (ccp1m3:ccp1m0 = 1011 ), this signal will reset timer3. timer3 must be configured for either timer, or synchro- nized counter mode, to take advantage of this feature. if timer3 is running in asynchronous counter mode, this reset operation may not work. in the event that a write to timer3 coincides with a special event trigger from ccp1, the write will take precedence. in this mode of operation, the ccpr1h:ccpr1l registers pair becomes the period register for timer3. refer to section 14.0, ? capture/compare/pwm (ccp) modules ? , for ccp details. table 13-1: registers associated with timer3 as a timer/counter note: the special event triggers from the ccp module will not set interrupt flag bit tmr3if (pir registers). name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets intcon gie/ gieh peie/ giel tmr0ie int0ie rbie tmr0if int0if rbif 0000 000x 0000 000u pir2 ? ? ? ? bclif lvdif tmr3if ccp2if ---- 0000 -0-- 0000 pie2 ? ? ? ? bclie lvdie tmr3ie ccp2ie ---- 0000 -0-- 0000 ipr2 ? ? ? ? bclip lvdip tmr3ip ccp2ip ---- 0000 -0-- 0000 tmr3l holding register for the least significant byte of the 16-bit tmr3 register xxxx xxxx uuuu uuuu tmr3h holding register for the most significant byte of the 16-bit tmr3 register xxxx xxxx uuuu uuuu t1con rd16 ? t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on 0-00 0000 u-uu uuuu t3con rd16 t3ccp2 t3ckps1 t3ckps0 t3ccp1 t3sync tmr3cs tmr3on 0000 0000 uuuu uuuu legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. shaded cells are not used by the timer3 module.
PIC18C601/801 ds39541a-page 140 advance information ? 2001 microchip technology inc. notes:
? 2001 microchip technology inc. advance information ds39541a-page 141 PIC18C601/801 14.0 capture/compare/pwm (ccp) modules each ccp (capture/compare/pwm) module contains a 16-bit register that can operate as a 16-bit capture register, as a 16-bit compare register, or as a pwm duty cycle register. table 14-1 shows the timer resources of the ccp module modes. the operation of ccp1 is identical to that of ccp2, with the exception of the special event trigger. therefore, operation of a ccp module in the following sections is described, with respect to ccp1. table 14-2 shows the interaction of the ccp modules. register 14-1 shows the ccpx control registers (ccpxcon). for the ccp1 module, the register is called ccp1con and for the ccp2 module, the regis- ter is called ccp2con. register 14-1: ccp1con register ccp2con register u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ccp1con ? ? dc1b1 dc1b0 ccp1m3 ccp1m2 ccp1m1 ccp1m0 bit 7 bit 0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ccp2con ? ? dc2b1 dc2b0 ccp2m3 ccp2m2 ccp2m1 ccp2m0 bit 7 bit 0 bit 7-6 unimplemented: read as '0' bit 5-4 dcxb1:dcxb0 : pwm duty cycle bit1 and bit0 capture mode: unused compare mode: unused pwm mode: these bits are the two lsbs (bit1 and bit0) of the 10-bit pwm duty cycle. the upper eight bits (dcx9:dcx2) of the duty cycle are found in ccprxl. bit 3-0 ccpxm3:ccpxm0 : ccpx mode select bits 0000 = capture/compare/pwm off (resets ccpx module) 0001 = reserved 0010 = compare mode, toggle output on match (ccpxif bit is set) 0011 = reserved 0100 = capture mode, every falling edge 0101 = capture mode, every rising edge 0110 = capture mode, every 4th rising edge 0111 = capture mode, every 16th rising edge 1000 = compare mode, initialize ccp pin low, on compare match force ccp pin high (ccpif bit is set) 1001 = compare mode, initialize ccp pin high, on compare match force ccp pin low (ccpif bit is set) 1010 = compare mode, generate software interrupt on compare match (ccpif bit is set, ccp pin is unaffected) 1011 = compare mode, trigger special event (ccpif bit is set, reset tmr1 or tmr3) 11xx = pwm mode legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown
PIC18C601/801 ds39541a-page 142 advance information ? 2001 microchip technology inc. 14.1 ccp1 module capture/compare/pwm register1 (ccpr1) is com- prised of two 8-bit registers: ccpr1l (low byte) and ccpr1h (high byte). the ccp1con register controls the operation of ccp1. all are readable and writable. 14.2 ccp2 module capture/compare/pwm register2 (ccpr2) is com- prised of two 8-bit registers: ccpr2l (low byte) and ccpr2h (high byte). the ccp2con register controls the operation of ccp2. all are readable and writable. table 14-1: ccp mode - timer resource 14.3 capture mode in capture mode, ccpr1h:ccpr1l captures the 16-bit value of the tmr1 or tmr3 registers, when an event occurs on pin rc2/ccp1. an event is defined as: every falling edge every rising edge every 4th rising edge every 16th rising edge an event is selected by control bits ccp1m3:ccp1m0 (ccp1con<3:0>). when a capture is made, the inter- rupt request flag bit ccp1if (pir registers) is set. it must be cleared in software. if another capture occurs before the value in register ccpr1 is read, the old cap- tured value will be lost. 14.3.1 ccp pin configuration in capture mode, the rc2/ccp1 pin should be config- ured as an input by setting the trisc<2> bit. 14.3.2 timer1/timer3 mode selection the timers used with the capture feature (either timer1 and/or timer3) must be running in timer mode or syn- chronized counter mode. in asynchronous counter mode, the capture operation may not work. the timer used with each ccp module is selected in the t3con register. table 14-2: interaction of two ccp modules ccp mode timer resource capture compare pwm timer1 or timer3 timer1 or timer3 timer2 note: if the rc2/ccp1 is configured as an out- put, a write to the port can cause a capture condition. ccpx mode ccpy mode interaction capture capture tmr1 or tmr3 time-base. time-base can be different for each ccp. capture compare the compare could be configured for the special event trigger, which clears either tmr1 or tmr3, depending upon which time-base is used. compare compare the compare(s) could be configured for the special event trigger, which clears tmr1 or tmr3, depending upon which time-base is used. pwm pwm the pwms will have the same frequency and update rate (tmr2 interrupt). pwm capture none. pwm compare none.
? 2001 microchip technology inc. advance information ds39541a-page 143 PIC18C601/801 14.3.3 software interrupt when the capture mode is changed, a false capture interrupt may be generated. the user should keep bit ccp1ie (pie registers) clear to avoid false interrupts and should clear the flag bit ccp1if, following any such change in operating mode. 14.3.4 ccp prescaler there are four prescaler settings, specified by bits ccp1m3:ccp1m0. whenever the ccp module is turned off, or the ccp module is not in capture mode, the prescaler counter is cleared. this means that any reset will clear the prescaler counter. switching from one capture prescaler to another may generate an interrupt. also, the prescaler counter will not be cleared; therefore, the first capture may be from a non-zero prescaler. example 14-1 shows the recom- mended method for switching between capture pres- calers. this example also clears the prescaler counter and will not generate the ? false ? interrupt. example 14-1: changing between capture prescalers figure 14-1: capture mode operation block diagram clrf ccp1con, f ; turn ccp module off movlw new_capt_ps ; load wreg with the ; new prescaler mode ; value and ccp on movwf ccp1con ; load ccp1con with ; this value ccpr1h ccpr1l tmr1h tmr1l set flag bit ccp1if tmr3 enable q ? s ccp1m3:ccp1m0 rc2/ccp1 pin prescaler 1, 4, 16 and edge detect tmr3h tmr3l tmr1 enable t3ccp2 t3ccp2 ccpr2h ccpr2l tmr1h tmr1l set flag bit ccp2if tmr3 enable q ? s ccp2m3:ccp2m0 rc1/ccp2 pin prescaler 1, 4, 16 and edge detect tmr3h tmr3l tmr1 enable t3ccp2 t3ccp1 t3ccp2 t3ccp1 rxb0if or rxb1if ccp1con<3:0> note: i/o pins have diode protection to v dd and v ss .
PIC18C601/801 ds39541a-page 144 advance information ? 2001 microchip technology inc. 14.4 compare mode in compare mode, the 16-bit ccpr1 (ccpr2) register value is constantly compared against either the tmr1 register pair value, or the tmr3 register pair value. when a match occurs, the rc2/ccp1 (rc1/ccp2) pin can have one of the following actions: driven high driven low toggle output (high to low or low to high) remains unchanged the action on the pin is based on the value of control bits ccp1m3:ccp1m0 (ccp2m3:ccp2m0). at the same time, interrupt flag bit ccp1if (ccp2if) is set. 14.4.1 ccp pin configuration the user must configure the ccpx pin as an output by clearing the appropriate trisc bit. 14.4.2 timer1/timer3 mode selection timer1 and/or timer3 must be running in timer mode, or synchronized counter mode, if the ccp module is using the compare feature. in asynchronous counter mode, the compare operation may not work. 14.4.3 software interrupt mode when generate software interrupt is chosen, the ccp1 pin is not affected. only a ccp interrupt is gen- erated (if enabled). 14.4.4 special event trigger in this mode, an internal hardware trigger is generated, which may be used to initiate an action. the special event trigger output of ccp1 resets the tmr1 register pair. this allows the ccpr1 register to effectively be a 16-bit programmable period register for timer1. the special trigger output of ccpx resets either the tmr1, or tmr3 register pair. additionally, the ccp2 special event trigger will start an a/d conversion, if the a/d module is enabled. figure 14-2: compare mode operation block diagram note: clearing the ccp1con register will force the rc2/ccp1 compare output latch to the default low level. this is not the data latch. note: the special event trigger from the ccp2 module will not set the timer1 or timer3 interrupt flag bits. ccpr1h ccpr1l tmr1h tmr1l comparator qs r output logic special event trigger set flag bit ccp1if match rc2/ccp1 trisc<2> ccp1m3:ccp1m0 mode select output enable pin special event trigger will: reset timer1 or timer3 (but not set timer1 or timer3 interrupt flag bit) set bit go/done, which starts an a/d conversion (ccp2 only) tmr3h tmr3l t3ccp2 ccpr2h ccpr2l comparator 1 0 t3ccp2 t3ccp1 qs r output logic special event trigger set flag bit ccp2if match rc1/ccp2 trisc<1> ccp2m3:ccp2m0 mode select output enable pin 01 note: i/o pins have diode protection to v dd and v ss .
? 2001 microchip technology inc. advance information ds39541a-page 145 PIC18C601/801 table 14-3: registers associated with capture, compare, timer1 and timer3 name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets intcon gie/ gieh peie/ giel tmr0ie int0ie rbie tmr0if int0if rbif 0000 000x 0000 000u pir1 ? adif rcif txif sspif ccp1if tmr2if tmr1if -000 0000 -000 0000 pie1 ? adie rcie txie sspie ccp1ie tmr2ie tmr1ie -000 0000 -000 0000 ipr1 ? adip rcip txip sspip ccp1ip tmr2ip tmr1ip -000 0000 -000 0000 trisc portc data direction register 1111 1111 1111 1111 tmr1l holding register for the least significant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu tmr1h holding register for the most significant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu t1con rd16 ? t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on 0-00 0000 u-uu uuuu ccpr1l capture/compare/pwm register1 (lsb) xxxx xxxx uuuu uuuu ccpr1h capture/compare/pwm register1 (msb) xxxx xxxx uuuu uuuu ccp1con ? ? dc1b1 dc1b0 ccp1m3 ccp1m2 ccp1m1 ccp1m0 --00 0000 --00 0000 ccpr2l capture/compare/pwm register2 (lsb) xxxx xxxx uuuu uuuu ccpr2h capture/compare/pwm register2 (msb) xxxx xxxx uuuu uuuu ccp2con ? ? dc2b1 dc2b0 ccp2m3 ccp2m2 ccp2m1 ccp2m0 --00 0000 --00 0000 pir2 ? ? ? ? bclif lvdif tmr3if ccp2if ---- 0000 ---- 0000 pie2 ? ? ? ? bclie lvdie tmr3ie ccp2ie ---- 0000 ---- 0000 ipr2 ? ? ? ? bclip lvdip tmr3ip ccp2ip ---- 0000 ---- 0000 tmr3l holding register for the least significant byte of the 16-bit tmr3 register xxxx xxxx uuuu uuuu tmr3h holding register for the most significant byte of the 16-bit tmr3 register xxxx xxxx uuuu uuuu t3con rd16 t3ccp2 t3ckps1 t3ckps0 t3ccp1 t3sync tmr3cs tmr3on 0000 0000 uuuu uuuu legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. shaded cells are not used by capture and timer1.
PIC18C601/801 ds39541a-page 146 advance information ? 2001 microchip technology inc. 14.5 pwm mode in pulse width modulation (pwm) mode, the ccp1 pin produces up to a 10-bit resolution pwm output. since the ccp1 pin is multiplexed with the portc data latch, the trisc<2> bit must be cleared to make the ccp1 pin an output. figure 14-3 shows a simplified block diagram of the ccp module in pwm mode. for a step-by-step procedure on how to setup the ccp module for pwm operation, see section 14.5.3. figure 14-3: simplified pwm block diagram a pwm output (figure 14-4) has a time-base (period) and a time that the output stays high (duty cycle). the frequency of the pwm is the inverse of the period (1/period). figure 14-4: pwm output 14.5.1 pwm period the pwm period is specified by writing to the pr2 register. the pwm period can be calculated by the formula: pwm period = [(pr2) + 1] ? 4 t osc (tmr2 prescale value) where pwm frequency is defined as 1 / [pwm period]. when tmr2 is equal to pr2, the following three events occur on the next increment cycle: tmr2 is cleared the ccp1 pin is set (exception: if pwm duty cycle = 0%, the ccp1 pin will not be set) the pwm duty cycle is latched from ccpr1l into ccpr1h 14.5.2 pwm duty cycle the pwm duty cycle is specified by writing to the ccpr1l register and to the ccp1con<5:4> bits. up to 10-bit resolution is available. the ccpr1l contains the eight msbs and the ccp1con<5:4> contains the two lsbs. this 10-bit value is represented by ccpr1l:ccp1con<5:4>. the following equation is used to calculate the pwm duty cycle in time: pwm duty cycle = (ccpr1l:ccp1con<5:4>) t osc (tmr2 prescale value) ccpr1l and ccp1con<5:4> can be written to at any time, but the duty cycle value is not latched into ccpr1h until after a match between pr2 and tmr2 occurs (i.e., the period is complete). in pwm mode, ccpr1h is a read-only register. the ccpr1h register and a 2-bit internal latch are used to double buffer the pwm duty cycle. this double buffering is essential for glitchless pwm operation. when the ccpr1h and 2-bit latch match tmr2, con- catenated with an internal 2-bit q clock or 2 bits of the tmr2 prescaler, the ccp1 pin is cleared. the maximum pwm resolution (bits) for a given pwm frequency is given by the equation: note: clearing the ccp1con register will force the ccp1 pwm output latch to the default low level. this is not the portc i/o data latch. ccpr1l (master) ccpr1h (slave) comparator tmr2 comparator pr2 (note 1) r q s duty cycle registers ccp1con<5:4> clear timer, ccp1 pin and latch d.c. trisc<2> rc2/ccp1 note 1: 8-bit timer is concatenated with 2-bit internal q clock, or 2 bits of the prescaler, to create 10-bit time-base. period duty cycle tmr2 = pr2 tmr2 = duty cycle tmr2 = pr2 note: the timer2 postscaler (see section 12.1) is not used in the determination of the pwm frequency. the postscaler could be used to have a servo update rate at a dif- ferent frequency than the pwm output. note: if the pwm duty cycle value is longer than the pwm period, the ccp1 pin will not be cleared. f osc f pwm --------------- ?? ?? log 2 () log ----------------------------- b i t s = pwm resolution (max)
? 2001 microchip technology inc. advance information ds39541a-page 147 PIC18C601/801 14.5.3 setup for pwm operation the following steps should be taken when configuring the ccp module for pwm operation: 1. set the pwm period by writing to the pr2 register. 2. set the pwm duty cycle by writing to the ccpr1l register and ccp1con<5:4> bits. 3. make the ccp1 pin an output by clearing the trisc<2> bit. 4. set the tmr2 prescale value and enable timer2 by writing to t2con. 5. configure the ccp1 module for pwm operation. table 14-4: example pwm frequencies and resolutions at 25 mhz table 14-5: registers associated with pwm and timer2 pwm frequency 1.53 khz 6.10 khz 24.41 khz 97.66khz 195.31 khz 260.42 khz timer prescaler (1, 4, 16) 16 4 1 1 1 1 pr2 value 0ffh ffh ffh 3fh 1fh 17h maximum resolution (bits) 10 10 10 8 7 6.6 name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets intcon gie/ gieh peie/ giel tmr0ie int0ie rbie tmr0if int0if rbif 0000 000x 0000 000u pir1 ? adif rcif txif sspif ccp1if tmr2if tmr1if -000 0000 -000 0000 pie1 ? adie rcie txie sspie ccp1ie tmr2ie tmr1ie -000 0000 -000 0000 ipr1 ? adip rcip txip sspip ccp1ip tmr2ip tmr1ip -000 0000 -000 0000 trisc portc data direction register 1111 1111 1111 1111 tmr2 timer2 module ? s register 0000 0000 0000 0000 pr2 timer2 module ? s period register 1111 1111 1111 1111 t2con ? toutps3 toutps2 toutps1 toutps0 tmr2on t2ckps1 t2ckps0 -000 0000 -000 0000 ccpr1l capture/compare/pwm register1 (lsb) xxxx xxxx uuuu uuuu ccpr1h capture/compare/pwm register1 (msb) xxxx xxxx uuuu uuuu ccp1con ? ? dc1b1 dc1b0 ccp1m3 ccp1m2 ccp1m1 ccp1m0 --00 0000 --00 0000 ccpr2l capture/compare/pwm register2 (lsb) xxxx xxxx uuuu uuuu ccpr2h capture/compare/pwm register2 (msb) xxxx xxxx uuuu uuuu ccp2con ? ? dc2b1 dc2b0 ccp2m3 ccp2m2 ccp2m1 ccp2m0 --00 0000 --00 0000 pir2 ? ? ? ? bclif lvdif tmr3if ccp2if ---- 0000 ---- 0000 pie2 ? ? ? ? bclie lvdie tmr3ie ccp2ie ---- 0000 ---- 0000 ipr2 ? ? ? ? bclip lvdip tmr3ip ccp2ip ---- 0000 ---- 0000 legend: x = unknown, u = unchanged, ? = unimplemented, read as '0'. shaded cells are not used by pwm and timer2.
PIC18C601/801 ds39541a-page 148 advance information ? 2001 microchip technology inc. notes:
? 2001 microchip technology inc. advance information ds39541a-page 149 PIC18C601/801 15.0 master synchronous serial port (mssp) module 15.1 master ssp (mssp) module overview the master synchronous serial port (mssp) module is a serial interface useful for communicating with other peripheral or microcontroller devices. these peripheral devices may be serial eeproms, shift registers, dis- play drivers, a/d converters, etc. the mssp module can operate in one of two modes: serial peripheral interface tm (spi) inter-integrated circuit tm (i 2 c) - full master mode - slave mode (with general address call) the i 2 c interface supports the following modes in hardware: master mode multi-master mode slave mode
PIC18C601/801 ds39541a-page 150 advance information ? 2001 microchip technology inc. 15.2 control registers the mssp module has three associated registers. these include a status register and two control registers. register 15-1 shows the mssp status register (sspstat), register 15-2 shows the mssp control register 1 (sspcon1), and register 15-3 shows the mssp control register 2 (sspcon2). register 15-1: sspstat register r/w-0 r/w-0 r-0 r-0 r-0 r-0 r-0 r-0 smp cke d/a psr/w ua bf bit 7 bit 0 bit 7 smp: sample bit spi master mode: 1 = input data sampled at end of data output time 0 = input data sampled at middle of data output time spi slave mode: smp must be cleared when spi is used in slave mode in i 2 c master or slave mode: 1 = slew rate control disabled for standard speed mode (100 khz and 1 mhz) 0 = slew rate control enabled for high speed mode (400 khz) bit 6 cke: spi clock edge select ckp = 0: 1 = data transmitted on rising edge of sck 0 = data transmitted on falling edge of sck ckp = 1 : 1 = data transmitted on falling edge of sck 0 = data transmitted on rising edge of sck bit 5 d/a : data/address bit (i 2 c mode only) 1 = indicates that the last byte received or transmitted was data 0 = indicates that the last byte received or transmitted was address bit 4 p: stop bit (i 2 c mode only. this bit is cleared when the mssp module is disabled, sspen is cleared.) 1 = indicates that a stop bit has been detected last (this bit is ? 0 ? on reset) 0 = stop bit was not detected last bit 3 s: start bit (i 2 c mode only. this bit is cleared when the mssp module is disabled, sspen is cleared.) 1 = indicates that a start bit has been detected last (this bit is ? 0 ? on reset) 0 = start bit was not detected last bit 2 r/w : read/write bit information (i 2 c mode only) this bit holds the r/w bit information following the last address match. this bit is only valid from the address match to the next start bit, stop bit, or not ack bit. in i 2 c slave mode: 1 = read 0 = write in i 2 c master mode: 1 = transmit is in progress 0 = transmit is not in progress. or-ing this bit with sen, rsen, pen, rcen, or acken will indicate if the mssp is in idle mode. bit 1 ua: update address (10-bit i 2 c mode only) 1 = indicates that the user needs to update the address in the sspadd register 0 = address does not need to be updated bit 0 bf: buffer full status bit receive (spi and i 2 c modes): 1 = receive complete, sspbuf is full 0 = receive not complete, sspbuf is empty transmit (i 2 c mode only): 1 = data transmit in progress (does not include the ack and stop bits), sspbuf is full 0 = data transmit complete (does not include the ack and stop bits), sspbuf is empty legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown
? 2001 microchip technology inc. advance information ds39541a-page 151 PIC18C601/801 register 15-2: sspcon1 register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 wcol sspov sspen ckp sspm3 sspm2 sspm1 sspm0 bit 7 bit 0 bit 7 wcol: write collision detect bit master mode: 1 = a write to the sspbuf register was attempted while the i 2 c conditions were not valid for a transmission to be started 0 = no collision slave mode: 1 = the sspbuf register is written while it is still transmitting the previous word (must be cleared in software) 0 = no collision bit 6 sspov: receive overflow indicator bit in spi mode: 1 = a new byte is received while the sspbuf register is still holding the previous data. in case of overflow, the data in sspsr is lost. overflow can only occur in slave mode. in slave mode, the user must read the sspbuf, even if only transmitting data, to avoid setting overflow. in master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the sspbuf register. (must be cleared in software.) 0 = no overflow in i 2 c mode: 1 = a byte is received while the sspbuf register is still holding the previous byte. sspov is a "don ? t care" in transmit mode. (must be cleared in software.) 0 = no overflow bit 5 sspen: synchronous serial port enable bit in both modes, when enabled, these pins must be properly configured as input or output. in spi mode: 1 = enables serial port and configures sck, sdo, sdi, and ss as the source of the serial port pins 0 = disables serial port and configures these pins as i/o port pins in i 2 c mode: 1 = enables the serial port and configures the sda and scl pins as the source of the serial port pins 0 = disables serial port and configures these pins as i/o port pins bit 4 ckp: clock polarity select bit in spi mode: 1 = idle state for clock is a high level 0 = idle state for clock is a low level in i 2 c slave mode: sck release control 1 = enable clock 0 = holds clock low (clock stretch). (used to ensure data setup time.) in i 2 c master mode: unused in this mode bit 3 - 0 sspm3:sspm0: synchronous serial port mode select bits 0000 = spi master mode, clock = f osc /4 0001 = spi master mode, clock = f osc /16 0010 = spi master mode, clock = f osc /64 0011 = spi master mode, clock = tmr2 output/2 0100 = spi slave mode, clock = sck pin. ss pin control enabled. 0101 = spi slave mode, clock = sck pin. ss pin control disabled. ss can be used as i/o pin. 0110 = i 2 c slave mode, 7-bit address 0111 = i 2 c slave mode, 10-bit address 1000 = i 2 c master mode, clock = f osc / (4 * (sspadd+1) ) 1001 = reserved 1010 = reserved 1011 = i 2 c firmware controlled master mode (slave idle) 1100 = reserved 1101 = reserved 1110 = i 2 c slave mode, 7-bit address with start and stop bit interrupts enabled 1111 = i 2 c slave mode, 10-bit address with start and stop bit interrupts enabled legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown
PIC18C601/801 ds39541a-page 152 advance information ? 2001 microchip technology inc. register 15-3: sspcon2 register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 gcen ackstat ackdt acken rcen pen rsen sen bit 7 bit 0 bit 7 gcen: general call enable bit (in i 2 c slave mode only) 1 = enable interrupt when a general call address (0000h) is received in the sspsr 0 = general call address disabled bit 6 ackstat: acknowledge status bit (in i 2 c master mode only) in master transmit mode: 1 = acknowledge was not received from slave 0 = acknowledge was received from slave bit 5 ackdt: acknowledge data bit (in i 2 c master mode only) in master receive mode: value transmitted when the user initiates an acknowledge sequence at the end of a receive 1 = not acknowledge 0 = acknowledge bit 4 acken: acknowledge sequence enable bit (in i 2 c master mode only) in master receive mode: 1 = initiate acknowledge sequence on sda and scl pins, and transmit ackdt data bit. automatically cleared by hardware. 0 = acknowledge sequence idle bit 3 rcen: receive enable bit (in i 2 c master mode only) 1 = enables receive mode for i 2 c 0 = receive idle bit 2 pen: stop condition enable bit (in i 2 c master mode only) sck release control 1 = initiate stop condition on sda and scl pins. automatically cleared by hardware. 0 = stop condition idle bit 1 rsen: repeated start condition enabled bit (in i 2 c master mode only) 1 = initiate repeated start condition on sda and scl pins. automatically cleared by hardware. 0 = repeated start condition idle bit 0 sen: start condition enabled bit (in i 2 c master mode only) 1 = initiate start condition on sda and scl pins. automatically cleared by hardware. 0 = start condition idle note: for bits acken, rcen, pen, rsen, sen: if the i 2 c module is not in the idle mode, this bit may not be set (no spooling) and the sspbuf may not be written (or writes to the sspbuf are disabled). legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown
? 2001 microchip technology inc. advance information ds39541a-page 153 PIC18C601/801 15.3 spi mode the spi mode allows 8 bits of data to be synchronously transmitted and received, simultaneously. all four modes of spi are supported. to accomplish communi- cation, typically three pins are used: serial data out (sdo) - rc5/sdo serial data in (sdi) - rc4/sdi/sda serial clock (sck) - rc3/sck/scl/lvoin additionally, a fourth pin may be used when in any slave mode of operation: slave select (ss ) - ra5/ss /an4 15.3.1 operation when initializing the spi, several options need to be specified. this is done by programming the appropriate control bits sspcon1<5:0> and sspstat<7:6>. these control bits allow the following to be specified: master mode (sck is the clock output) slave mode (sck is the clock input) clock polarity (idle state of sck) data input sample phase (middle or end of data output time) clock edge (output data on rising/falling edge of sck) clock rate (master mode only) slave select mode (slave mode only) figure 15-1 shows the block diagram of the mssp module, when in spi mode. figure 15-1: mssp block diagram (spi mode) ( ) read write internal data bus sspsr reg sspm3:sspm0 bit0 shift clock ss control enable edge select clock select tmr2 output t osc prescaler 4, 16, 64 2 edge select 2 4 data to tx/rx in sspsr tris bit 2 smp:cke sdi sdo ss sck note: i/o pins have diode protection to v dd and v ss . sspbuf reg
PIC18C601/801 ds39541a-page 154 advance information ? 2001 microchip technology inc. the mssp consists of a transmit/receive shift register (sspsr) and a buffer register (sspbuf). the sspsr shifts the data in and out of the device, msb first. the sspbuf holds the data that was written to the sspsr, until the received data is ready. once the 8 bits of data have been received, that byte is moved to the sspbuf register. then the buffer full detect bit, bf (sspstat register), and the interrupt flag bit, sspif (pir regis- ters), are set. this double buffering of the received data (sspbuf) allows the next byte to start reception before reading the data that was just received. any write to the sspbuf register during transmission/reception of data will be ignored, and the write collision detect bit, wcol (sspcon1 register), will be set. user software must clear the wcol bit so that it can be determined if the following write(s) to the sspbuf register completed successfully. when the application software is expecting to receive valid data, the sspbuf should be read before the next byte of data to transfer is written to the sspbuf. the buffer full (bf) bit (sspstat register) indicates when sspbuf has been loaded with the received data (transmission is complete). when the sspbuf is read, the bf bit is cleared. this data may be irrelevant if the spi is only a transmitter. generally, the mssp interrupt is used to determine when the transmission/reception has completed. the sspbuf must be read and/or written. if the interrupt method is not going to be used, then software polling can be done to ensure that a write collision does not occur. example 15-1 shows the loading of the sspbuf (sspsr) for data transmission. the sspsr is not directly readable or writable, and can only be accessed by addressing the sspbuf reg- ister. additionally, the mssp status register (sspstat register) indicates the various status conditions. 15.3.2 enabling spi i/o to enable the serial port, ssp enable bit, sspen (sspcon1 register), must be set. to reset or reconfig- ure spi mode, clear the sspen bit, re-initialize the sspcon registers, and then set the sspen bit. this configures the sdi, sdo, sck, and ss pins as serial port pins. for the pins to behave as the serial port func- tion, corresponding pins must have their data direction bits (in the tris register) appropriately programmed. that is: sdi is automatically controlled by the spi module sdo must have trisc<5> bit cleared sck (master mode) must have trisc<3> bit cleared sck (slave mode) must have trisc<3> bit set ra5 must be configured as digital i/o using adcon1 register ss must have trisa<5> bit set any serial port function that is not desired may be overridden by programming the corresponding data direction (tris) register to the opposite value. example 15-1: loading the sspbuf (sspsr) register loop btfss sspstat, bf ;has data been received (transmit complete)? bra loop ;no movf sspbuf, w ;wreg reg = contents of sspbuf movwf rxdata ;save in user ram, if data is meaningful movf txdata, w ;w reg = contents of txdata movwf sspbuf ;new data to xmit
? 2001 microchip technology inc. advance information ds39541a-page 155 PIC18C601/801 15.3.3 master mode the master can initiate the data transfer at any time because it controls the sck. the master determines when the slave is to broadcast data by the software protocol. in master mode, the data is transmitted/received as soon as the sspbuf register is written to. if the spi is only going to receive, the sdo output could be dis- abled (programmed as an input). the sspsr register will continue to shift in the signal present on the sdi pin at the programmed clock rate. as each byte is received, it will be loaded into the sspbuf register as a normal received byte (interrupts and status bits appropriately set). this could be useful in receiver applications as a ? line activity monitor ? mode. the clock polarity is selected by appropriately program- ming the ckp bit (sspcon1 register). this, then, would give waveforms for spi communication as shown in figure 15-2, figure 15-4, and figure 15-5, where the msb is transmitted first. in master mode, the spi clock rate (bit rate) is user programmable to be one of the following: f osc /4 (or t cy ) f osc /16 (or 4 t cy ) f osc /64 (or 16 t cy ) timer2 output/2 this allows a maximum data rate (at 25 mhz) of 6.25 mbps. figure 15-2 shows the waveforms for master mode. when the cke bit is set, the sdo data is valid before there is a clock edge on sck. the change of the input sample is shown based on the state of the smp bit. the time when the sspbuf is loaded with the received data is shown. figure 15-2: spi mode waveform (master mode) sck (ckp = 0 sck (ckp = 1 sck (ckp = 0 sck (ckp = 1 4 clock modes input sample input sample sdi bit7 bit0 sdo bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit0 sdi sspif (smp = 1) (smp = 0) (smp = 1) cke = 1) cke = 0) cke = 1) cke = 0) (smp = 0) write to sspbuf sspsr to sspbuf sdo bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 (cke = 0) (cke = 1) next q4 cycle after q2
PIC18C601/801 ds39541a-page 156 advance information ? 2001 microchip technology inc. 15.3.4 slave mode in slave mode, the data is transmitted and received as the external clock pulses appear on sck. when the last bit is latched, the sspif interrupt flag bit is set. while in slave mode, the external clock is supplied by the external clock source on the sck pin. this external clock must meet the minimum high and low times, as specified in the electrical specifications. while in sleep mode, the slave can transmit/receive data. when a byte is received, the device will wake-up from sleep. 15.3.5 slave select synchronization the ss pin allows a synchronous slave mode. the spi must be in slave mode with ss pin control enabled (sspcon1<3:0> = 04h). the pin must not be driven low for the ss pin to function as an input. the data latch must be high. when the ss pin is low, transmission and reception are enabled and the sdo pin is driven. when the ss pin goes high, the sdo pin is no longer driven, even if in the mid- dle of a transmitted byte, and becomes a floating output. external pull-up/pull-down resistors may be desirable, depending on the application. when the spi module resets, the bit counter is forced to 0. this can be done by either forcing the ss pin to a high level, or clearing the sspen bit. to emulate two-wire communication, the sdo pin can be connected to the sdi pin. when the spi needs to operate as a receiver, the sdo pin can be configured as an input. this disables transmissions from the sdo. the sdi can always be left as an input (sdi function), since it cannot create a bus conflict. figure 15-3: slave synchronization waveform note 1: when the spi is in slave mode with ss pin control enabled, (sspcon<3:0> = 0100 ), the spi module will reset if the ss pin is set to v dd . 2: if the spi is used in slave mode with cke set, then the ss pin control must be enabled. sck (ckp = 1 sck (ckp = 0 input sample sdi bit7 sdo bit7 bit6 bit7 sspif (smp = 0) cke = 0) cke = 0) (smp = 0) write to sspbuf sspsr to sspbuf ss bit0 bit7 bit0 next q4 cycle after q2
? 2001 microchip technology inc. advance information ds39541a-page 157 PIC18C601/801 figure 15-4: spi mode waveform (slave mode with cke = 0) figure 15-5: spi mode waveform (slave mode with cke = 1) sck (ckp = 1 sck (ckp = 0 input sample sdi bit7 bit0 sdo bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sspif (smp = 0) cke = 0) cke = 0) (smp = 0) write to sspbuf sspsr to sspbuf ss optional next q4 cycle after q2 sck (ckp = 1 sck (ckp = 0 input sample sdi bit7 bit0 sdo bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sspif (smp = 0) cke = 1) cke = 1) (smp = 0) write to sspbuf sspsr to sspbuf ss required next q4 cycle after q2
PIC18C601/801 ds39541a-page 158 advance information ? 2001 microchip technology inc. 15.3.6 sleep operation in master mode, all module clocks are halted, and the transmission/reception will remain in that state until the device wakes from sleep. after the device returns to normal mode, the module will continue to transmit/ receive data. in slave mode, the spi transmit/receive shift register operates asynchronously to the device. this allows the device to be placed in sleep mode, and data to be shifted into the spi transmit/receive shift register. when all eight bits have been received, the mssp interrupt flag bit will be set and, if enabled, will wake the device from sleep. 15.3.7 effects of a reset a reset disables the mssp module and terminates the current transfer. 15.3.8 bus mode compatibility table 15-1 shows the compatibility between the stan- dard spi modes and the states of the ckp and cke control bits. table 15-1: spi bus modes there is also a smp bit that controls when the data will be sampled. table 15-2: registers associated with spi operation standard spi mode terminology control bits state ckp cke 0, 0 01 0, 1 00 1, 0 11 1, 1 10 name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets intcon gie/ gieh peie/ giel tmr0ie int0ie rbie tmr0if int0if rbif 0000 000x 0000 000u pir1 ? adif rcif txif sspif ccp1if tmr2if tmr1if -000 0000 -000 0000 pie1 ? adie rcie txie sspie ccp1ie tmr2ie tmr1ie -000 0000 -000 0000 ipr1 ? adip rcip txip sspip ccp1ip tmr2ip tmr1ip -000 0000 -000 0000 trisc portc data direction register 1111 1111 1111 1111 sspbuf synchronous serial port receive buffer/transmit register xxxx xxxx uuuu uuuu sspcon wcol sspov sspen ckp sspm3 sspm2 sspm1 sspm0 0000 0000 0000 0000 trisa ? porta data direction register --11 1111 --11 1111 sspstat smp cke d/a p s r/w ua bf 0000 0000 0000 0000 legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. shaded cells are not used by the mssp in spi mode.
? 2001 microchip technology inc. advance information ds39541a-page 159 PIC18C601/801 15.4 mssp i 2 c operation the mssp module in i 2 c mode, fully implements all master and slave functions (including general call sup- port) and provides interrupts on start and stop bits in hardware to determine a free bus (multi-master mode). the mssp module implements the standard mode specifications, as well as 7-bit and 10-bit addressing. two pins are used for data transfer. these are the rc3/ sck/scl pin, which is the clock (scl), and the rc4/ sdi/sda pin, which is the data (sda). the user must configure these pins as inputs or outputs through the trisc<4:3> bits. the mssp module functions are enabled by setting mssp enable bit sspen (sspcon1 register). the mssp module has these six registers for i 2 c oper- ation: mssp control register1 (sspcon1) mssp control register2 (sspcon2) mssp status register (sspstat) serial receive/transmit buffer (sspbuf) mssp shift register (sspsr) - not directly accessible mssp address register (sspadd) figure 15-6: mssp block diagram (i 2 c mode) the sspcon1 register allows control of the i 2 c oper- ation. the sspm3:sspm0 mode selection bits (sspcon1 register) allow one of the following i 2 c modes to be selected: i 2 c master mode, clock = osc/(4*(sspadd +1)) i 2 c slave mode (7-bit address) i 2 c slave mode (10-bit address) i 2 c slave mode (7-bit address), with start and stop bit interrupts enabled i 2 c slave mode (10-bit address), with start and stop bit interrupts enabled i 2 c firmware controlled master operation, slave is idle selection of any i 2 c mode with the sspen bit set, forces the scl and sda pins to be open drain, pro- vided these pins are programmed to inputs by setting the appropriate trisc bits. 15.4.1 slave mode in slave mode, the scl and sda pins must be config- ured as inputs (trisc<4:3> set). the mssp module will override the input state with the output data when required (slave-transmitter). when an address is matched, or the data transfer after an address match is received, the hardware automati- cally will generate the acknowledge (ack ) pulse and load the sspbuf register with the received value cur- rently in the sspsr register. if either or both of the following conditions are true, the mssp module will not give this ack pulse: a) the buffer full bit bf (sspcon1 register) was set before the transfer was received. b) the overflow bit sspov (sspcon1 register) was set before the transfer was received. in this event, the sspsr register value is not loaded into the sspbuf, but bit sspif (pir registers) is set. the bf bit is cleared by reading the sspbuf register, while bit sspov is cleared through software. the scl clock input must have a minimum high and low for proper operation. the high and low times of the i 2 c specification, as well as the requirement of the mssp module, is shown in timing parameter #100 and parameter #101. read write sspsr reg match detect sspadd reg start and stop bit detect sspbuf reg internal data bus addr match set, reset s, p bits (sspstat reg) rc3/sck/scl rc4/ shift clock msb sdi/ lsb sda note: i/o pins have diode protection to v dd and v ss .
PIC18C601/801 ds39541a-page 160 advance information ? 2001 microchip technology inc. 15.4.1.1 addressing once the mssp module has been enabled, it waits for a start condition to occur. following the start con- dition, the eight bits are shifted into the sspsr register. all incoming bits are sampled with the rising edge of the clock (scl) line. the value of register sspsr<7:1> is compared to the value of the sspadd register. the address is compared on the falling edge of the eighth clock (scl) pulse. if the addresses match, and the bf and sspov bits are clear, the following events occur: a) the sspsr register value is loaded into the sspbuf register. b) the buffer full bit bf is set. c) an ack pulse is generated. d) mssp interrupt flag bit sspif (pir registers) is set on the falling edge of the ninth scl pulse (interrupt is generated, if enabled). in 10-bit address mode, two address bytes need to be received by the slave. the five most significant bits (msb) of the first address byte, specify if this is a 10-bit address. the r/w bit (sspstat register) must specify a write so the slave device will receive the second address byte. for a 10-bit address, the first byte would equal ?1111 0 a9 a8 0? , where a9 and a8 are the two msb ? s of the address. the sequence of events for 10-bit addressing is as fol- lows, with steps 7- 9 for slave-transmitter: 1. receive first (high) byte of address (the sspif, bf and ua bits (sspstat register) are set). 2. update the sspadd register with second (low) byte of address (clears bit ua and releases the scl line). 3. read the sspbuf register (clears bit bf) and clear flag bit sspif. 4. receive second (low) byte of address (bits sspif, bf, and ua are set). 5. update the sspadd register with the first (high) byte of address. if match releases scl line, this will clear bit ua. 6. read the sspbuf register (clears bit bf) and clear flag bit sspif. 7. receive repeated start condition. 8. receive first (high) byte of address (bits sspif and bf are set). 9. read the sspbuf register (clears bit bf) and clear flag bit sspif. 15.4.1.2 reception when the r/w bit of the address byte is clear and an address match occurs, the r/w bit of the sspstat register is cleared. the received address is loaded into the sspbuf register. when the address byte overflow condition exists, then no acknowledge (ack ) pulse is given. an overflow con- dition is defined as either bit bf (sspstat register) is set or bit sspov (sspcon1 register) is set. an mssp interrupt is generated for each data transfer byte. flag bit sspif (pir registers) must be cleared in software. the sspstat register is used to determine the status of the byte. 15.4.1.3 transmission when the r/w bit of the incoming address byte is set and an address match occurs, the r/w bit of the sspstat register is set. the received address is loaded into the sspbuf register. the ack pulse will be sent on the ninth bit and pin rc3/sck/scl is held low. the transmit data must be loaded into the sspbuf register, which also loads the sspsr regis- ter. then pin rc3/sck/scl should be enabled by set- ting bit ckp (sspcon1 register). the master must monitor the scl pin prior to asserting another clock pulse. the slave devices may be holding off the master by stretching the clock. the eight data bits are shifted out on the falling edge of the scl input. this ensures that the sda signal is valid during the scl high time (figure 15-8). an mssp interrupt is generated for each data transfer byte. the sspif bit must be cleared in software and the sspstat register is used to determine the status of the byte. the sspif bit is set on the falling edge of the ninth clock pulse. as a slave-transmitter, the ack pulse from the master- receiver is latched on the rising edge of the ninth scl input pulse. if the sda line is high (not ack ), then the data transfer is complete. when the ack is latched by the slave, the slave logic is reset (resets sspstat reg- ister) and the slave monitors for another occurrence of the start bit. if the sda line was low (ack ), the trans- mit data must be loaded into the sspbuf register, which also loads the sspsr register. pin rc3/sck/scl should be enabled by setting bit ckp.
? 2001 microchip technology inc. advance information ds39541a-page 161 PIC18C601/801 figure 15-7: i 2 c slave mode waveforms for reception (7-bit address) figure 15-8: i 2 c slave mode waveforms for transmission (7-bit address) p 9 8 7 6 5 d0 d1 d2 d3 d4 d5 d6 d7 s a7 a6 a5 a4 a3 a2 a1 sda scl 123456 789 1234 56 7 89 1234 bus master term ina tes transfer bit sspov is set because the sspbuf register is still full. cleared in software sspbuf register is read ack receiving data receiving data d0 d1 d2 d3 d4 d5 d6 d7 ack r/w = 0 receiving address sspif bf sspov not ack ack is not sent. sda scl sspif bf ckp a7 a6 a5 a4 a3 a2 a1 ack d7 d6 d5 d4 d3 d2 d1 d0 not ack transmitting data r/w = 1 receiving address 123456789 123456789 p cleared in software sspbuf is written in software from ssp interrupt service routine set bit after writing to sspbuf s data in sampled scl held low while cpu responds to sspif (the sspbuf must be written to before the ckp bit can be set) r/w = 0
PIC18C601/801 ds39541a-page 162 advance information ? 2001 microchip technology inc. 15.4.2 general call address support the addressing procedure for the i 2 c bus is such that the first byte after the start condition usually deter- mines which device will be the slave addressed by the master. the exception is the general call address, which can address all devices. when this address is used, all devices should, in theory, respond with an acknowledge. the general call address is one of eight addresses reserved for specific purposes by the i 2 c protocol. it consists of all 0 ? s with r/w = 0. the general call address is recognized (enabled) when the general call enable (gcen) bit is set (sspcon2 register). following a start bit detect, eight bits are shifted into the sspsr and the address is compared against the sspadd. it is also compared to the general call address and fixed in hardware. if the general call address matches, the sspsr is transferred to the sspbuf, the bf bit is set (eighth bit), and on the falling edge of the ninth bit (ack bit), the sspif interrupt flag bit is set. when the interrupt is serviced, the source for the inter- rupt can be checked by reading the contents of the sspbuf. the value can be used to determine if the address was device specific or a general call address. in 10-bit mode, the sspadd is required to be updated for the second half of the address to match, and the ua bit is set (sspstat register). if the general call address is sampled when the gcen bit is set and while the slave is configured in 10-bit address mode, then the second half of the address is not necessary. the ua bit will not be set, and the slave will begin receiving data after the acknowledge (figure 15-9). figure 15-9: slave mode general call address sequence (7 or 10-bit address) sda scl s sspif bf sspov cleared in software sspbuf is read r/w = 0 ack general call address address is compared to general call address gcen receiving data ack 123456789123456789 d7 d6 d5 d4 d3 d2 d1 d0 after ack, set interrupt ? 0 ? ? 1 ?
? 2001 microchip technology inc. advance information ds39541a-page 163 PIC18C601/801 15.4.3 master mode master mode of operation is supported by interrupt generation on the detection of the start and stop conditions. the stop (p) and start (s) bits are cleared from a reset, or when the mssp module is disabled. control of the i 2 c bus may be taken when the p bit is set, or the bus is idle, with both the s and p bits clear. in master mode, the scl and sda lines are manipu- lated by the mssp hardware. the following events will cause ssp interrupt flag bit, sspif, to be set (ssp interrupt if enabled): start condition stop condition data transfer byte transmitted/received acknowledge transmit repeated start condition 15.4.4 i 2 c master mode support master mode is enabled by setting and clearing the appropriate sspm bits in sspcon1 and by setting the sspen bit. once master mode is enabled, the user has the following six options: 1. assert a start condition on sda and scl. 2. assert a repeated start condition on sda and scl. 3. write to the sspbuf register initiating transmis- sion of data/address. 4. generate a stop condition on sda and scl. 5. configure the i 2 c port to receive data. 6. generate an acknowledge condition at the end of a received byte of data. figure 15-10: mssp block diagram (i 2 c master mode) note: the mssp module, when configured in i 2 c master mode, does not allow queueing of events. for instance, the user is not allowed to initiate a start condition and immediately write the sspbuf register to imitate transmission, before the start condition is complete. in this case, the sspbuf will not be written to and the wcol bit will be set, indicating that a write to the sspbuf did not occur. read write sspsr start bit, stop bit, sspbuf internal data bus set/reset, s, p, wcol (sspstat) shift clock msb lsb sda acknowledge generate scl scl in bus collision sda in receive enable clock cntl clock arbitrate/wcol detect (hold off clock source) sspadd<6:0> baud set sspif, bclif reset ackstat, pen (sspcon2) rate generator sspm3:sspm0 note: i/o pins have diode protection to v dd and v ss . start bit detect stop bit detect write collision detect clock arbitration state counter for end of xmit/rcv
PIC18C601/801 ds39541a-page 164 advance information ? 2001 microchip technology inc. 15.4.4.1 i 2 c master mode operation the master device generates all of the serial clock pulses and the start and stop conditions. a trans- fer is ended with a stop condition or with a repeated start condition. since the repeated start condi- tion is also the beginning of the next serial transfer, the i 2 c bus will not be released. in master transmitter mode, serial data is output through sda, while scl outputs the serial clock. the first byte transmitted contains the slave address of the receiving device (7 bits) and the read/write (r/w ) bit. in this case, the r/w bit will be logic ? 0 ? . serial data is transmitted eight bits at a time. after each byte is trans- mitted, an acknowledge bit is received. start and stop conditions are output to indicate the beginning and the end of a serial transfer. in master receive mode, the first byte transmitted con- tains the slave address of the transmitting device (7 bits) and the r/w bit. in this case, the r/w bit will be logic ? 1 ? . thus, the first byte transmitted is a 7-bit slave address followed by a ? 1 ? to indicate receive bit. serial data is received via sda, while scl outputs the serial clock. serial data is received eight bits at a time. after each byte is received, an acknowledge bit is transmit- ted. start and stop conditions indicate the begin- ning and end of transmission. the baud rate generator used for the spi mode opera- tion is now used to set the scl clock frequency for either 100 khz, 400 khz, or 1 mhz i 2 c operation. the baud rate generator reload value is contained in the lower 7 bits of the sspadd register. the baud rate generator will automatically begin counting on a write to the sspbuf. once the given operation is complete (i.e., transmission of the last data bit is followed by ack), the internal clock will automatically stop counting and the scl pin will remain in its last state. a typical transmit sequence would go as follows: a) the user generates a start condition by set- ting the start enable (sen) bit (sspcon2 register). b) sspif is set. the mssp module will wait the required start time before any other operation takes place. c) the user loads the sspbuf with the address to transmit. d) address is shifted out the sda pin until all eight bits are transmitted. e) the mssp module shifts in the ack bit from the slave device and writes its value into the ackstat bit (sspcon2 register). f) the mssp module generates an interrupt at the end of the ninth clock cycle by setting the sspif bit. g) the user loads the sspbuf with eight bits of data. h) data is shifted out the sda pin until all eight bits are transmitted. i) the mssp module shifts in the ack bit from the slave device and writes its value into the ackstat bit (sspcon2 register). j) the mssp module generates an interrupt at the end of the ninth clock cycle by setting the sspif bit. k) the user generates a stop condition by setting the stop enable bit pen (sspcon2 register). l) interrupt is generated once the stop condition is complete. 15.4.5 baud rate generator in i 2 c master mode, the reload value for the brg is located in the lower 7 bits of the sspadd register (figure 15-11). when the brg is loaded with this value, the brg counts down to 0 and stops until another reload has taken place. the brg count is dec- remented twice per instruction cycle (t cy ) on the q2 and q4 clocks. in i 2 c master mode, the brg is reloaded automatically. if clock arbitration is taking place, for instance, the brg will be reloaded when the scl pin is sampled high (figure 15-12). figure 15-11: baud rate generator block diagram sspm3:sspm0 brg down counter clkout f osc /4 sspadd<6:0> sspm3:sspm0 scl reload control reload
? 2001 microchip technology inc. advance information ds39541a-page 165 PIC18C601/801 figure 15-12: baud rate generator timing with clock arbitration 15.4.6 i 2 c master mode start condition timing to initiate a start condition, the user sets the start condition enable (sen) bit (sspcon2 register). if the sda and scl pins are sampled high, the baud rate generator is re-loaded with the contents of sspadd<6:0> and starts its count. if scl and sda are both sampled high when the baud rate generator times out (t brg ), the sda pin is driven low. the action of the sda being driven low while scl is high, is the start condition, and causes the s bit (sspstat register) to be set. following this, the baud rate generator is reloaded with the contents of sspadd<6:0> and resumes its count. when the baud rate generator times out (t brg ), the sen bit (sspcon2 register) will be automatically cleared by hardware, the baud rate gen- erator is suspended leaving the sda line held low and the start condition is complete. 15.4.6.1 wcol status flag if the user writes the sspbuf when a start sequence is in progress, the wcol is set and the con- tents of the buffer are unchanged (the write doesn ? t occur). figure 15-13: first start bit timing sda scl scl de-asserted but slave holds dx-1 dx brg scl is sampled high, reload takes place and brg starts its count 03h 02h 01h 00h (hold off) 03h 02h reload brg value scl low (clock arbitration) scl allowed to transition high brg decrements on q2 and q4 cycles note: if at the beginning of the start condition, the sda and scl pins are already sam- pled low, or if during the start condition the scl line is sampled low before the sda line is driven low, a bus collision occurs, the bus collision interrupt flag bclif is set, the start condition is aborted, and the i 2 c module is reset into its idle state. note: because queueing of events is not allowed, writing to the lower 5 bits of sspcon2 is disabled until the start condition is complete. sda scl s t brg 1st bit 2nd bit t brg sda = 1, at completion of start bit, scl = 1 write to sspbuf occurs here t brg hardware clears sen bit t brg write to sen bit occurs here set s bit (sspstat) and sets sspif bit
PIC18C601/801 ds39541a-page 166 advance information ? 2001 microchip technology inc. 15.4.7 i 2 c master mode repeated start condition timing a repeated start condition occurs when the rsen bit (sspcon2 register) is programmed high and the i 2 c logic module is in the idle state. when the rsen bit is set, the scl pin is asserted low. when the scl pin is sampled low, the baud rate generator is loaded with the contents of sspadd<5:0> and begins count- ing. the sda pin is released (brought high) for one baud rate generator count (t brg ). when the baud rate generator times out, if sda is sampled high, the scl pin will be de-asserted (brought high). when scl is sam- pled high, the baud rate generator is re-loaded with the contents of sspadd<6:0> and begins counting. sda and scl must be sampled high for one t brg . this action is then followed by assertion of the sda pin (sda = 0) for one t brg , while scl is high. following this, the rsen bit (sspcon2 register) will be automatically cleared and the baud rate generator will not be reloaded, leaving the sda pin held low. as soon as a start con- dition is detected on the sda and scl pins, the s bit (sspstat register) will be set. the sspif bit will not be set until the baud rate generator has timed out. immediately following the sspif bit getting set, the user may write the sspbuf with the 7-bit address in 7-bit mode, or the default first address in 10-bit mode. after the first eight bits are transmitted and an ack is received, the user may then transmit an additional eight bits of address (10-bit mode) or eight bits of data (7-bit mode). 15.4.7.1 wcol status flag if the user writes the sspbuf when a repeated start sequence is in progress, the wcol is set and the contents of the buffer are unchanged (the write doesn ? t occur). figure 15-14: repeated start condition waveform note 1: if rsen is programmed while any other event is in progress, it will not take effect. 2: a bus collision during the repeated start condition occurs, if: sda is sampled low when scl goes from low to high. scl goes low before sda is asserted low. this may indicate that another master is attempting to transmit a data "1". note: because queueing of events is not allowed, writing of the lower 5 bits of sspcon2 is disabled until the repeated start condition is complete. sda scl sr = repeated start write to sspcon2 write to sspbuf occurs here falling edge of ninth clock end of xmit at completion of start bit, hardware clear rsen bit 1st bit set s (sspstat<3>) t brg t brg sda = 1, sda = 1, scl (no change) scl = 1 occurs here. t brg t brg t brg and set sspif
? 2001 microchip technology inc. advance information ds39541a-page 167 PIC18C601/801 15.4.8 i 2 c master mode transmission transmission of a data byte, a 7-bit address, or the other half of a 10-bit address, is accomplished by sim- ply writing a value to the sspbuf register. this action will set the buffer full bit, bf, and allow the baud rate generator to begin counting and start the next transmis- sion. each bit of address/data will be shifted out onto the sda pin after the falling edge of scl is asserted (see data hold time specification parameter 106). scl is held low for one baud rate generator rollover count (t brg ). data should be valid before scl is released high (see data setup time specification parameter 107). when the scl pin is released high, it is held that way for t brg . the data on the sda pin must remain stable for that duration and some hold time after the next fall- ing edge of scl. after the eighth bit is shifted out (the falling edge of the eighth clock), the bf bit is cleared and the master releases sda, allowing the slave device being addressed to respond with an ack bit during the ninth bit time, if an address match occurs, or if data was received properly. the status of ack is writ- ten into the ackdt bit on the falling edge of the ninth clock. if the master receives an acknowledge, the acknowledge status bit, ackstat, is cleared; if not, the bit is set. after the ninth clock, the sspif bit is set and the master clock (baud rate generator) is suspended until the next data byte is loaded into the sspbuf, leaving scl low and sda unchanged (figure 15-15). after the write to the sspbuf, each bit of address will be shifted out on the falling edge of scl, until all seven address bits and the r/w bit, are completed. on the falling edge of the eighth clock, the master will de- assert the sda pin, allowing the slave to respond with an acknowledge. on the falling edge of the ninth clock, the master will sample the sda pin to see if the address was recognized by a slave. the status of the ack bit is loaded into the ackstat status bit (sspcon2 register). following the falling edge of the ninth clock transmission of the address, the sspif is set, the bf bit is cleared and the baud rate generator is turned off, until another write to the sspbuf takes place, holding scl low and allowing sda to float. 15.4.8.1 bf status flag in transmit mode, the bf bit (sspstat register) is set when the cpu writes to sspbuf, and is cleared when all eight bits are shifted out. 15.4.8.2 wcol status flag if the user writes the sspbuf when a transmit is already in progress (i.e., sspsr is still shifting out a data byte), the wcol is set and the contents of the buffer are unchanged (the write doesn ? t occur). wcol must be cleared in software. 15.4.8.3 ackstat status flag in transmit mode, the ackstat bit (sspcon2 register) is cleared when the slave has sent an acknowledge (ack = 0), and is set when the slave does not acknowledge (ack = 1). a slave sends an acknowledge when it has recognized its address (including a general call), or when the slave has properly received its data. 15.4.9 i 2 c master mode reception master mode reception is enabled by programming the receive enable bit, rcen (sspcon2 register). the baud rate generator begins counting and on each rollover, the state of the scl pin changes (high to low/ low to high) and data is shifted into the sspsr. after the falling edge of the eighth clock, the rcen bit is automatically cleared, the contents of the sspsr are loaded into the sspbuf, the bf bit is set, the sspif flag bit is set and the baud rate generator is suspended from counting, holding scl low. the mssp is now in idle state, awaiting the next command. when the buffer is read by the cpu, the bf bit is automatically cleared. the user can then send an acknowledge bit at the end of reception, by setting the acknowledge sequence enable bit acken (sspcon2 register). 15.4.9.1 bf status flag in receive operation, the bf bit is set when an address or data byte is loaded into sspbuf from sspsr. it is cleared when the sspbuf register is read. 15.4.9.2 sspov status flag in receive operation, the sspov bit is set when eight bits are received into the sspsr and the bf bit is already set from a previous reception. 15.4.9.3 wcol status flag if the user writes the sspbuf when a receive is already in progress (i.e., sspsr is still shifting in a data byte), the wcol bit is set and the contents of the buffer are unchanged (the write doesn ? t occur). note: the mssp module must be in an idle state before the rcen bit is set, or the rcen bit will be disregarded.
PIC18C601/801 ds39541a-page 168 advance information ? 2001 microchip technology inc. figure 15-15: i 2 c master mode waveform (transmission, 7 or 10-bit address) sda scl sspif bf sen a7 a6 a5 a4 a3 a2 a1 ack = 0 d7d6d5d4d3d2d1d0 ack transmitting data or second half r/w = 0 transmit address to slave 123456789 123456789 p cleared in software service routine sspbuf is written in software from ssp interrupt after start condition, sen cleared by hardware. s sspbuf written with 7-bit address and r/w start transmit scl held low while cpu responds to sspif sen = 0 of 10-bit address write sspcon2<0> sen = 1 start condition begins from slave, clear ackstat bit sspcon2<6> ackstat in sspcon2 = 1 cleared in software sspbuf written pen cleared in software r/w
? 2001 microchip technology inc. advance information ds39541a-page 169 PIC18C601/801 figure 15-16: i 2 c master mode waveform (reception, 7-bit address) p 9 8 7 6 5 d0 d1 d2 d3 d4 d5 d6 d7 s a7 a6 a5 a4 a3 a2 a1 sda scl 12 3 4 5 6 7 8 9 12 3 4 5 678 9 1234 bus master terminates transfer ack receiving data from slave receiving data from slave d0 d1 d2 d3 d4 d5 d6 d7 ack r/w = 1 transmit address to slave sspif bf ack is not sent write to sspcon2<0> (sen = 1) write to sspbuf occurs here ack from slave master configured as a receiver by programming sspcon2<3>, (rcen = 1) pen bit = 1 written here data shifted in on falling edge of clk cleared in software start xmit sen = 0 sspov sda = 0, scl = 1 while cpu ack last bit is shifted into sspsr and contents are unloaded into sspbuf cleared in software cleared in software set sspif interrupt at end of receive set p bit (sspstat<4>) and sspif cleared in software ack from master set sspif at end set sspif interrupt at end of acknowledge sequence set sspif interrupt at end of acknow- ledge sequence of receive set acken, start acknowledge sequence sspov is set because sspbuf is still full sda = ackdt = 1 rcen cleared automatically rcen = 1 start next receive write to sspcon2<4> to start acknowledge sequence sda = ackdt (sspcon2<5>) = 0 rcen cleared automatically responds to sspif acken begin start condition cleared in software sda = ackdt = 0
PIC18C601/801 ds39541a-page 170 advance information ? 2001 microchip technology inc. 15.4.10 acknowledge sequence timing an acknowledge sequence is enabled by setting the acknowledge sequence enable bit, acken (sspcon2 register). when this bit is set, the scl pin is pulled low and the contents of the acknowledge data bit (ackdt) is presented on the sda pin. if the user wishes to gen- erate an acknowledge, then the ackdt bit should be cleared. if not, the user should set the ackdt bit before starting an acknowledge sequence. the baud rate gen- erator then counts for one rollover period (t brg ) and the scl pin is de-asserted (pulled high). when the scl pin is sampled high (clock arbitration), the baud rate gener- ator counts for t brg . the scl pin is then pulled low. fol- lowing this, the acken bit is automatically cleared, the baud rate generator is turned off and the mssp module then goes into idle mode (figure 15-17). 15.4.10.1 wcol status flag if the user writes the sspbuf when an acknowledge sequence is in progress, then wcol is set and the con- tents of the buffer are unchanged (the write doesn ? t occur). 15.4.11 stop condition timing a stop bit is asserted on the sda pin at the end of a receive/transmit by setting the stop sequence enable bit, pen (sspcon2 register). at the end of a receive/ transmit, the scl line is held low after the falling edge of the ninth clock. when the pen bit is set, the master will assert the sda line low. when the sda line is sam- pled low, the baud rate generator is reloaded and counts down to 0. when the baud rate generator times out, the scl pin will be brought high, and one t brg (baud rate generator rollover count) later, the sda pin will be de-asserted. when the sda pin is sampled high while scl is high, the p bit (sspstat register) is set. a t brg later, the pen bit is cleared and the sspif bit is set (figure 15-18). 15.4.11.1 wcol status flag if the user writes the sspbuf when a stop sequence is in progress, then the wcol bit is set and the contents of the buffer are unchanged (the write doesn ? t occur). figure 15-17: acknowledge sequence waveform figure 15-18: stop condition receive or transmit mode note: t brg = one baud rate generator period. sda scl set sspif at the end acknowledge sequence starts here, write to sspcon2 acken automatically cleared cleared in t brg t brg of receive ack 8 acken = 1, ackdt = 0 d0 9 sspif software set sspif at the end of acknowledge sequence cleared in software scl sda sda asserted low before rising edge of clock write to sspcon2 set pen falling edge of scl = 1 for t brg , followed by sda = 1 for t brg 9th clock scl brought high after t brg t brg t brg after sda sampled high, p bit (sspstat) is set t brg to set up stop condition ack p t brg pen bit (sspcon2) is cleared by hardware and the sspif bit is set note: t brg = one baud rate generator period.
? 2001 microchip technology inc. advance information ds39541a-page 171 PIC18C601/801 15.4.12 clock arbitration clock arbitration occurs when the master, during any receive, transmit or repeated start/stop condition, de-asserts the scl pin (scl allowed to float high). when the scl pin is allowed to float high, the baud rate generator (brg) is suspended from counting until the scl pin is actually sampled high. when the scl pin is sampled high, the baud rate generator is reloaded with the contents of sspadd<6:0> and begins counting. this ensures that the scl high time will always be at least one brg rollover count, in the event that the clock is held low by an external device (figure 15-19). 15.4.13 sleep operation while in sleep mode, the i 2 c module can receive addresses or data, and when an address match or complete byte transfer occurs, wake the processor from sleep (if the mssp interrupt is enabled). 15.4.14 effect of a reset a reset disables the mssp module and terminates the current transfer. figure 15-19: clock arbitration timing in master transmit mode scl sda brg overflow, release scl, if scl = 1, load brg with sspadd<6:0> and start count brg overflow occurs, release scl, slave device holds scl low. scl = 1 brg starts counting clock high interval. scl line sampled once every machine cycle (t osc 2 4). hold off brg until scl is sampled high. t brg t brg t brg to measure high time interval
PIC18C601/801 ds39541a-page 172 advance information ? 2001 microchip technology inc. 15.4.15 multi-master mode in multi-master mode, the interrupt generation on the detection of the start and stop conditions allows the determination of when the bus is free. the stop (p) and start (s) bits are cleared from a reset, or when the mssp module is disabled. control of the i 2 c bus may be taken when the p bit (sspstat register) is set, or the bus is idle, with both the s and p bits clear. when the bus is busy, enabling the ssp interrupt will generate the interrupt when the stop condition occurs. in multi-master operation, the sda line must be moni- tored for arbitration, to see if the signal level is the expected output level. this check is performed in hard- ware, with the result placed in the bclif bit. arbitration can be lost in the following states: address transfer data transfer a start condition a repeated start condition an acknowledge condition 15.4.16 multi -master communication, bus collision, and bus arbitration multi-master mode support is achieved by bus arbitra- tion. when the master outputs address/data bits onto the sda pin, arbitration takes place when the master outputs a '1' on sda, by letting sda float high and another master asserts a '0'. when the scl pin floats high, data should be stable. if the expected data on sda is a '1' and the data sampled on the sda pin = '0', then a bus collision has taken place. the master will set the bus collision interrupt flag (bclif) and reset the i 2 c port to its idle state. (figure 15-20). if a transmit was in progress when the bus collision occurred, the transmission is halted, the bf bit is cleared, the sda and scl lines are de-asserted, and the sspbuf can be written to. when the user services the bus collision interrupt service routine, and if the i 2 c bus is free, the user can resume communication by asserting a start condition. if a start, repeated start, stop, or acknowledge condition was in progress when the bus collision occurred, the condition is aborted, the sda and scl lines are de-asserted, and the respective control bits in the sspcon2 register are cleared. when the user ser- vices the bus collision interrupt service routine, and if the i 2 c bus is free, the user can resume communication by asserting a start condition. the master will continue to monitor the sda and scl pins. if a stop condition occurs, the sspif bit will be set. a write to the sspbuf will start the transmission of data at the first data bit, regardless of where the trans- mitter left off when the bus collision occurred. in multi-master mode, the interrupt generation on the detection of start and stop conditions allows the determination of when the bus is free. control of the i 2 c bus can be taken when the p bit is set in the sspstat register, or the bus is idle and the s and p bits are cleared. figure 15-20: bus collision timing for transmit and acknowledge sda scl bclif sda released sda line pulled low by another source sample sda. while scl is high, data doesn ? t match what is driven bus collision has occurred. set bus collision interrupt (bclif) by the master. by master data changes while scl = 0
? 2001 microchip technology inc. advance information ds39541a-page 173 PIC18C601/801 15.4.16.1 bus collision during a start condition during a start condition, a bus collision occurs if: a) sda or scl are sampled low at the beginning of the start condition (figure 15-21). b) scl is sampled low before sda is asserted low (figure 15-22). during a start condition, both the sda and the scl pins are monitored. if the sda pin is already low, or the scl pin is already low, then all of the following occur: the start condition is aborted; the bclif flag is set, and the mssp module is reset to its idle state (figure 15-21). the start condition begins with the sda and scl pins de-asserted. when the sda pin is sampled high, the baud rate generator is loaded from sspadd<6:0> and counts down to 0. if the scl pin is sampled low while sda is high, a bus collision occurs, because it is assumed that another master is attempting to drive a data '1' during the start condition. if the sda pin is sampled low during this count, the brg is reset and the sda line is asserted early (figure 15-23). if, however, a '1' is sampled on the sda pin, the sda pin is asserted low at the end of the brg count. the baud rate generator is then reloaded and counts down to 0, and during this time, if the scl pin is sampled as '0', a bus collision does not occur. at the end of the brg count, the scl pin is asserted low. figure 15-21: bus collision during start condition (sda only) note: the reason that bus collision is not a factor during a start condition, is that no two bus masters can assert a start condition at the exact same time. therefore, one master will always assert sda before the other. this condition does not cause a bus collision, because the two masters must be allowed to arbitrate the first address follow- ing the start condition. if the address is the same, arbitration must be allowed to continue into the data portion, repeated start or stop conditions. sda scl sen sda sampled low before sda goes low before the sen bit is set. s bit and sspif set because ssp module reset into idle state. sen cleared automatically because of bus collision. s bit and sspif set because set sen, enable start condition if sda = 1, scl=1 sda = 0, scl = 1. bclif s sspif sda = 0, scl = 1. sspif and bclif are cleared in software. sspif and bclif are cleared in software. . set bclif, set bclif. start condition.
PIC18C601/801 ds39541a-page 174 advance information ? 2001 microchip technology inc. figure 15-22: bus collision during start condition (scl = 0) figure 15-23: brg reset due to sda arbitration during start condition sda scl sen bus collision occurs, set bclif scl = 0 before sda = 0, set sen, enable start sequence if sda = 1, scl = 1 t brg t brg sda = 0, scl = 1 bclif s sspif interrupt cleared in software bus collision occurs, set bclif scl = 0 before brg time-out, ? 0 ?? 0 ? ? 0 ? ? 0 ? sda scl sen set s set sen, enable start sequence if sda = 1, scl = 1 less than t brg t brg sda = 0, scl = 1 bclif s sspif s interrupts cleared in software set sspif sda = 0, scl = 1 sda pulled low by other master. reset brg and assert sda. scl pulled low after brg time-out set sspif ? 0 ?
? 2001 microchip technology inc. advance information ds39541a-page 175 PIC18C601/801 15.4.16.2 bus collision during a repeated start condition during a repeated start condition, a bus collision occurs if: a) a low level is sampled on sda when scl goes from low level to high level. b) scl goes low before sda is asserted low, indicating that another master is attempting to transmit a data ? 1 ? . when the user de-asserts sda and the pin is allowed to float high, the brg is loaded with sspadd<6:0> and counts down to 0. the scl pin is then de-asserted and when sampled high, the sda pin is sampled. if sda is low, a bus collision has occurred (i.e., another master is attempting to transmit a data ? 0 ? , see figure 15-24). if sda is sampled high, the brg is reloaded and begins counting. if sda goes from high to low before the brg times out, no bus collision occurs because no two masters can assert sda at exactly the same time. if scl goes from high to low before the brg times out and sda has not already been asserted, a bus collision occurs. in this case, another master is attempting to transmit a data ? 1 ? during the repeated start condi- tion (figure 15-25). if, at the end of the brg time-out both scl and sda are still high, the sda pin is driven low and the brg is reloaded and begins counting. at the end of the count, regardless of the status of the scl pin, the scl pin is driven low and the repeated start condition is complete. figure 15-24: bus collision during a repeated start condition (case 1) figure 15-25: bus collision during repeated start condition (case 2) sda scl rsen bclif s sspif sample sda when scl goes high. if sda = 0, set bclif and release sda and scl. cleared in software '0' '0' sda scl bclif rsen s sspif interrupt cleared in software scl goes low before sda. set bclif, release sda and scl. t brg t brg ? 0 ?
PIC18C601/801 ds39541a-page 176 advance information ? 2001 microchip technology inc. 15.4.16.3 bus collision during a stop condition bus collision occurs during a stop condition if: a) after the sda pin has been de-asserted and allowed to float high, sda is sampled low after the brg has timed out. b) after the scl pin is de-asserted, scl is sam- pled low before sda goes high. the stop condition begins with sda asserted low. when sda is sampled low, the scl pin is allowed to float. when the pin is sampled high (clock arbitration), the baud rate generator is loaded with sspadd<6:0> and counts down to 0. after the brg times out, sda is sampled. if sda is sampled low, a bus collision has occurred. this is due to another master attempting to drive a data ? 0 ? (figure 15-26). if the scl pin is sampled low before sda is allowed to float high, a bus collision occurs. this is another case of another master attempt- ing to drive a data ? 0 ? (figure 15-27). figure 15-26: bus collision during a stop condition (case 1) figure 15-27: bus collision during a stop condition (case 2) sda scl bclif pen p sspif t brg t brg t brg sda asserted low sda sampled low after t brg , set bclif ? 0 ? ? 0 ? sda scl bclif pen p sspif t brg t brg t brg assert sda scl goes low before sda goes high, set bclif ? 0 ? ? 0 ?
? 2001 microchip technology inc. advance information ds39541a-page 177 PIC18C601/801 16.0 addressable universal synchronous asynchronous receiver transmitter (usart) the universal synchronous asynchronous receiver transmitter (usart) module is one of the two serial i/o modules. (usart is also known as a serial com- munications interface or sci.) the usart can be con- figured as a full duplex asynchronous system that can communicate with peripheral devices, such as crt ter- minals and personal computers, or it can be configured as a half duplex synchronous system that can commu- nicate with peripheral devices, such as a/d or d/a inte- grated circuits, serial eeproms, etc. the usart can be configured in the following modes: asynchronous (full duplex) synchronous - master (half duplex) synchronous - slave (half duplex) the spen (rcsta register) and the trisc<7> bits have to be set, and the trisc<6> bit must be cleared, in order to configure pins rc6/tx/ck and rc7/rx/dt as the universal synchronous asynchro- nous receiver transmitter. register 16-1 shows the transmit status and control register (txsta) and register 16-2 shows the receive status and control register (rcsta). register 16-1: txsta register r/w-0 r/w-0 r/w-0 r/w-0 u-0 r/w-0 r-1 r/w-0 csrc tx9 txen sync ? brgh trmt tx9d bit 7 bit 0 bit 7 csrc: clock source select bit asynchronous mode: don ? t care synchronous mode: 1 = master mode (clock generated internally from brg) 0 = slave mode (clock from external source) bit 6 tx9 : 9-bit transmit enable bit 1 = selects 9-bit transmission 0 = selects 8-bit transmission bit 5 txen : transmit enable bit 1 = transmit enabled 0 = transmit disabled sren/cren overrides txen in sync mode. bit 4 sync : usart mode select bit 1 = synchronous mode 0 = asynchronous mode bit 3 unimplemented: read as '0' bit 2 brgh : high baud rate select bit asynchronous mode: 1 = high speed 0 = low speed synchronous mode: unused in this mode bit 1 trmt : transmit shift register status bit 1 = tsr empty 0 = tsr full bit 0 tx9d: 9th bit of transmit data. can be address/data bit or a parity bit. legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown
PIC18C601/801 ds39541a-page 178 advance information ? 2001 microchip technology inc. register 16-2: rcsta register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r-0 r-0 r-x spen rx9 sren cren adden ferr oerr rx9d bit 7 bit 0 bit 7 spen: serial port enable bit 1 = serial port enabled (configures rx/dt and tx/ck pins as serial port pins) 0 = serial port disabled bit 6 rx9 : 9-bit receive enable bit 1 = selects 9-bit reception 0 = selects 8-bit reception bit 5 sren : single receive enable bit asynchronous mode: don ? t care synchronous mode - master: 1 = enables single receive 0 = disables single receive this bit is cleared after reception is complete. synchronous mode - slave: unused in this mode bit 4 cren : continuous receive enable bit asynchronous mode: 1 = enables continuous receive 0 = disables continuous receive synchronous mode: 1 = enables continuous receive until enable bit cren is cleared (cren overrides sren) 0 = disables continuous receive bit 3 adden : address detect enable bit asynchronous mode 9-bit (rx9 = 1): 1 = enables address detection, enable interrupt and load of the receive buffer when rsr<8> is set 0 = disables address detection, all bytes are received, and ninth bit can be used as parity bit bit 2 ferr : framing error bit 1 = framing error (can be updated by reading rcreg register and receive next valid byte) 0 = no framing error bit 1 oerr : overrun error bit 1 = overrun error (can be cleared by clearing bit cren) 0 = no overrun error bit 0 rx9d: 9th bit of received data. can be address/data bit or a parity bit. legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown
? 2001 microchip technology inc. advance information ds39541a-page 179 PIC18C601/801 16.1 usart baud rate generator (brg) the brg supports both the asynchronous and syn- chronous modes of the usart. it is a dedicated 8-bit baud rate generator. the spbrg register controls the period of a free running 8-bit timer. in asynchronous mode, bit brgh (txsta register) also controls the baud rate. in synchronous mode, bit brgh is ignored. table 16-1 shows the formula for computation of the baud rate for different usart modes, which only apply in master mode (internal clock). given the desired baud rate and f osc , the nearest integer value for the spbrg register can be calculated using the formula in table 16-1. from this, the error in baud rate can be determined. example 16-1 shows the calculation of the baud rate error for the following conditions: f osc = 16 mhz desired baud rate = 9600 brgh = 0 sync = 0 it may be advantageous to use the high baud rate (brgh = 1), even for slower baud clocks. this is because the f osc /(16(x + 1)) equation can reduce the baud rate error in some cases. writing a new value to the spbrg register causes the brg timer to be reset (or cleared). this ensures the brg does not wait for a timer overflow before output- ting the new baud rate. 16.1.1 sampling the data on the rc7/rx/dt pin is sampled three times by a majority detect circuit to determine if a high or a low level is present at the rx pin. example 16-1: calculating baud rate error table 16-1: baud rate formula table 16-2: registers associated with baud rate generator desired baud rate = f osc / (64 (x + 1)) solving for x: x = ( (f osc / desired baud rate) / 64 ) - 1 x = ((16000000 / 9600) / 64) - 1 x = [25.042] = 25 calculated baud rate = 16000000 / (64 (25 + 1)) = 9615 error = (calculated baud rate - desired baud rate) desired baud rate = (9615 - 9600) / 9600 = 0.16% sync brgh = 0 (low speed) brgh = 1 (high speed) 0 1 (asynchronous) baud rate = f osc /(64(x+1)) (synchronous) baud rate = f osc /(4(x+1)) baud rate = f osc /(16(x+1)) na legend: x = value in spbrg (0 to 255) name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets txsta csrc tx9 txen sync ? brgh trmt tx9d 0000 -010 0000 -010 rcsta spen rx9 sren cren adden ferr oerr rx9d 0000 000x 0000 000x spbrg baud rate generator register 0000 0000 0000 0000 legend: x = unknown, - = unimplemented, read as '0'. shaded cells are not used by the brg.
PIC18C601/801 ds39541a-page 180 advance information ? 2001 microchip technology inc. table 16-3: baud rates for synchronous mode baud rate (kbps) f osc =25 mhz 20 mhz kbaud % error spbrg value (decimal) kbaud % error spbrg value (decimal) 0.3na- - na- - 1.2na- - na- - 2.4na- - na- - 9.6na- - na- - 19.2na- - na- - 76.8 77.16 +0.47 80 76.92 +0.16 64 96 96.15 +0.16 64 96.15 +0.16 51 300 297.62 -0.79 20 294.12 -1.96 16 500 480.77 -3.85 12 500 0 9 high 6250 - 0 5000 - 0 low 24.41 - 255 19.53 - 255 baud rate (kbps) f osc = 16 mhz 10 mhz 7.15909 mhz 5.0688 mhz kbaud % error spbrg value (decimal) kbaud % error spbrg value (decimal) kbaud % error spbrg value (decimal) kbaud % error spbrg value (decimal) 0.3na- - na- - na - - na- - 1.2na- - na- - na - - na- - 2.4na- - na- - na - - na- - 9.6 na - - na - - 9.62 +0.23 185 9.60 0 131 19.2 19.23 +0.16 207 19.23 +0.16 129 19.24 +0.23 92 19.20 0 65 76.8 76.92 +0.16 51 75.76 -1.36 32 77.82 +1.32 22 74.54 -2.94 16 96 95.24 -0.79 41 96.15 +0.16 25 94.20 -1.88 18 97.48 +1.54 12 300 307.70 +2.56 12 312.50 +4.17 7 298.35 -0.57 5 na - - 500 500 0 7 500 0 4 na - - na - - high 4000 - 0 2500 - 0 1789.80 - 0 1267.20 - 0 low 15.63 - 255 9.77 - 255 6.99 - 255 4.95 - 255 baud rate (kbps) f osc = 4 mhz 3.579545 mhz 1 mhz 32.768 khz kbaud % error spbrg value (decimal) kbaud % error spbrg value (decimal) kbaud % error spbrg value (decimal) kbaud % error spbrg value (decimal) 0.3 na - na - na - 0.30 +1.14 1.2 na - - na - - 1.20 +0.16 207 1.17 -2.48 6 2.4 na - - na - - 2.40 +0.16 103 na - - 9.6 9.62 +0.16 103 9.62 +0.23 92 9.62 +0.16 25 na - - 19.2 19.23 +0.16 51 19.04 -0.83 46 19.23 +0.16 12 na - - 76.8 76.92 +0.16 12 74.57 -2.90 11 na - - na - - 96 1000 +4.17 9 99.43 +3.57 8 na - - na - - 300 na - - 298.30 -0.57 2 na - - na - - 500 500 0 1 na - - na - - na - - high 1000 - 0 894.89 - 0 250 - 0 8.20 - 0 low 3.91 - 255 3.50 - 255 0.98 - 255 0.03 - 255
? 2001 microchip technology inc. advance information ds39541a-page 181 PIC18C601/801 table 16-4: baud rates for asynchronous mode (brgh = 0) baud rate (kbps) f osc = 25 mhz 20 mhz kbaud % error spbrg value (decimal) kbaud % error spbrg value (decimal) 0.3 na - na - 1.2 na - - na - - 2.4 2.40 -0.15 162 2.40 +0.16 129 9.6 9.53 -0.76 40 9.47 -1.36 32 19.2 19.53 +1.73 19 19.53 +1.73 15 76.8 78.13 +1.73 4 78.13 +1.73 3 96 97.66 +1.73 3 na - - 300 na - - 312.50 +4.17 0 500 na - - na - - high 390.63 - 0 312.50 - 0 low 1.53 - 255 1.22 - 255 baud rate (kbps) f osc = 16 mhz 10 mhz 7.15909 mhz 5.0688 mhz kbaud % error spbrg value (decimal) kbaud % error spbrg value (decimal) kbaud % error spbrg value (decimal) kbaud % error spbrg value (decimal) 0.3 na - na - na - na - 1.2 1.20 +0.16 207 1.20 +0.16 129 1.20 +0.23 92 1.20 0 65 2.4 2.40 +0.16 103 2.40 +0.16 64 2.38 -0.83 46 2.40 0 32 9.6 9.62 +0.16 25 9.77 +1.73 15 9.32 -2.90 11 9.90 +3.13 7 19.2 19.23 +0.16 12 19.53 +1.73 7 18.64 -2.90 5 19.80 +3.13 3 76.8 na - - 78.13 +1.73 1 na - - 79.20 +3.13 0 96 na - - na - - na - - na - - 300 na - - na - - na - - na - - 500 na - - na - - na - - na - - high 250 - 0 156.25 - 0 111.86 - 0 79.20 - 0 low 0.98 - 255 0.61 - 255 0.44 - 255 0.31 - 255 baud rate (kbps) f osc = 4 mhz 3.579545 mhz 1 mhz 32.768 khz kbaud % error spbrg value (decimal) kbaud % error spbrg value (decimal) kbaud % error spbrg value (decimal) kbaud % error spbrg value (decimal) 0.3 0.30 -0.16 0.30 +0.23 0.30 +0.16 na - 1.2 1.20 +1.67 51 1.19 -0.83 46 1.20 +0.16 12 na - - 2.4 2.40 +1.67 25 2.43 +1.32 22 na - - na - - 9.6 na - - 9.32 -2.90 5 na - - na - - 19.2 na - - 18.64 -2.90 2 na - - na - - 76.8 na - - na - - na - - na - - 96 na - - na - - na - - na - - 300 na - - na - - na - - na - - 500 na - - na - - na - - na - - high 62.50 - 0 55.93 - 0 15.63 - 0 0.51 - 0 low 0.24 - 255 0.22 - 255 0.06 - 255 0.002 - 255
PIC18C601/801 ds39541a-page 182 advance information ? 2001 microchip technology inc. table 16-5: baud rates for asynchronous mode (brgh = 1) baud rate (kbps) f osc = 25 mhz 20 mhz kbaud % error spbrg value (decimal) kbaud % error spbrg value (decimal) 0.3 na - na - 1.2 na - - na - - 2.4 na - - na - - 9.6 9.59 -0.15 162 9.62 +0.16 129 19.2 19.30 +0.47 80 19.23 +0.16 64 76.8 78.13 +1.73 19 78.13 +1.73 15 96 97.66 +1.73 15 96.15 +0.16 12 300 312.50 +4.17 4 312.50 +4.17 3 500 520.83 +4.17 2 na - - high 1562.50 - 0 1250 - 0 low 6.10 - 255 4.88 - 255 baud rate (kbps) f osc = 16 mhz 10 mhz 7.15909 mhz 5.0688 mhz kbaud % error spbrg value (decimal) kbaud % error spbrg value (decimal) kbaud % error spbrg value (decimal) kbaud % error spbrg value (decimal) 0.3na- na- na- na- 1.2na- - na- - na- - na- - 2.4 na - - na - - 2.41 +0.23 185 2.40 0 131 9.6 9.62 +0.16 103 9.62 +0.16 64 9.52 -0.83 46 9.60 0 32 19.2 19.23 +0.16 51 18.94 -1.36 32 19.45 +1.32 22 18.64 -2.94 16 76.8 76.92 +0.16 12 78.13 +1.73 7 74.57 -2.90 5 79.20 +3.13 3 96 100 +4.17 9 na - - na - - na - - 300 na - - 312.50 +4.17 1 na - - na - - 500 500 0 1 na - - na - - na - - high 1000 - 0 625 - 0 447.44 - 0 316.80 - 0 low 3.91 - 255 2.44 - 255 1.75 - 255 1.24 - 255 baud rate (kbps) f osc = 4 mhz 3.579545 mhz 1 mhz 32.768 khz kbaud % error spbrg value (decimal) kbaud % error spbrg value (decimal) kbaud % error spbrg value (decimal) kbaud % error spbrg value (decimal) 0.3 na - - na - - 0.30 +0.16 207 0.29 -2.48 6 1.2 1.20 +0.16 207 1.20 +0.23 185 1.20 +0.16 51 na - - 2.4 2.40 +0.16 103 2.41 +0.23 92 2.40 +0.16 25 na - - 9.6 9.62 +0.16 25 9.73 +1.32 22 na - - na - - 19.2 19.23 +0.16 12 18.64 -2.90 11 na - - na - - 76.8 na - - 74.57 -2.90 2 na - - na - - 96 na - - na - - na - - na - - 300na- - na- - na- - na- - 500na- - na- - na- - na- - high 250 - 0 55.93 - 0 62.50 - 0 2.05 - 0 low 0.98 - 255 0.22 - 255 0.24 - 255 0.008 - 255
? 2001 microchip technology inc. advance information ds39541a-page 183 PIC18C601/801 16.2 usart asynchronous mode in this mode, data is transmitted in non-return-to-zero (nrz) format. data consists of one start bit, eight or nine data bits and one stop bit. data is transmitted in serial fashion with lsb first. an on-chip 8-bit baud rate generator can be programmed to generate the desired baud rate. the baud rate generator produces a clock, either x16 or x64 of the bit shift rate, depending on the brgh bit (txsta register). usart does not automat- ically calculate the parity bit for the given data byte. if parity is to be transmitted, usart must be pro- grammed to transmit nine bits and software must set/ clear ninth data bit as parity bit. asynchronous mode is stopped during sleep. asynchronous mode is selected by clearing the sync bit (txsta register). the usart asynchronous module consists of the fol- lowing important elements: baud rate generator sampling circuit asynchronous transmitter asynchronous receiver 16.2.1 usart asynchronous transmitter the usart transmitter block diagram is shown in figure 16-1. the heart of the transmitter is the transmit (serial) shift register (tsr). the tsr register obtains its data from the read/write transmit buffer register (txreg). the txreg register is loaded with data in software. the tsr register is not loaded until the stop bit has been transmitted from the previous load. as soon as the stop bit is transmitted, the tsr is loaded with new data from the txreg register (if available). once the txreg register transfers the data to the tsr register (occurs in one t cy ), the txreg register is empty and flag bit txif (pir registers) is set. this inter- rupt can be enabled/disabled by setting/clearing enable bit txie (pie registers). flag bit txif will be set, regardless of the state of enable bit txie and can- not be cleared in software. it will reset only when new data is loaded into the txreg register. while flag bit txif indicated the status of the txreg register, another bit trmt (txsta register) shows the status of the tsr register. status bit trmt is a read only bit, which is set when the tsr register is empty. no inter- rupt logic is tied to this bit, so the user has to poll this bit in order to determine if the tsr register is empty. steps to follow when setting up an asynchronous transmission: 1. initialize the spbrg register for the appropriate baud rate. if a high speed baud rate is desired, set bit brgh (section 16.1). 2. enable the asynchronous serial port by clearing bit sync and setting bit spen. 3. if interrupts are desired, set enable bit txie. 4. if 9-bit transmission is desired, set transmit bit tx9. can be used as address/data bit. 5. enable the transmission by setting bit txen, which will also set bit txif. 6. if 9-bit transmission is selected, the ninth bit should be loaded in bit tx9d. 7. load data to the txreg register (starts trans- mission). figure 16-1: usart transmit block diagram note 1: the tsr register is not mapped in data memory, so it is not available to the user. 2: flag bit txif is set when enable bit txen is set. txif txie interrupt txen baud rate clk spbrg baud rate generator tx9d msb lsb data bus txreg register tsr register (8) 0 tx9 trmt spen rc6/tx/ck pin pin buffer and control 8 ? ? ? note: i/o pins have diode protection to v dd and v ss .
PIC18C601/801 ds39541a-page 184 advance information ? 2001 microchip technology inc. figure 16-2: asynchronous transmission figure 16-3: asynchronous transmission (back to back) table 16-6: registers associated with asynchronous transmission word 1 stop bit word 1 transmit shift reg start bit bit 0 bit 1 bit 7/8 write to txreg word 1 brg output (shift clock) rc6/tx/ck (pin) txif bit (transmit buffer register empty flag) trmt bit (transmit shift register empty flag) transmit shift reg. write to txreg brg output (shift clock) rc6/tx/ck (pin) txif bit (interrupt reg. flag) trmt bit (transmit shift reg. empty flag) word 1 word 2 word 1 word 2 start bit stop bit start bit transmit shift reg. word 1 word 2 bit 0 bit 1 bit 7/8 bit 0 note: this timing diagram shows two consecutive transmissions. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 0000 000x 0000 000u pir1 ? adif rcif txif sspif ccp1if tmr2if tmr1if -000 0000 -000 0000 pie1 ? adie rcie txie sspie ccp1ie tmr2ie tmr1ie -000 0000 -000 0000 ipr1 ? adip rcip txip sspip ccp1ip tmr2ip tmr1ip -000 0000 -000 0000 rcsta spen rx9 sren cren ? ferr oerr rx9d 0000 -00x 0000 -00x txreg usart transmit register 0000 0000 0000 0000 txsta csrc tx9 txen sync adden brgh trmt tx9d 0000 0010 0000 0010 spbrg baud rate generator register 0000 0000 0000 0000 legend: x = unknown, - = unimplemented locations read as '0'. shaded cells are not used for asynchronous transmission.
? 2001 microchip technology inc. advance information ds39541a-page 185 PIC18C601/801 16.2.2 usart asynchronous receiver the receiver block diagram is shown in figure 16-4. the data is received on the rc7/rx/dt pin and drives the data recovery block. the data recovery block is actually a high speed shifter, operating at x16 times the baud rate, whereas the main receive serial shifter oper- ates at the bit rate or at f osc . this mode would typi- cally be used in rs-232 systems. steps to follow when setting up an asynchronous reception: 1. initialize the spbrg register for the appropriate baud rate. if a high speed baud rate is desired, set bit brgh (section 16.1). 2. enable the asynchronous serial port by clearing bit sync and setting bit spen. 3. if interrupts are desired, set enable bit rcie. 4. if 9-bit reception is desired, set bit rx9. 5. enable the reception by setting bit cren. 6. flag bit rcif will be set when reception is com- plete and an interrupt will be generated if enable bit rcie was set. 7. read the rcsta register to get the ninth bit (if enabled) and determine if any error occurred during reception. 8. read the 8-bit received data by reading the rcreg register. 9. if any error occurred, clear the error by clearing enable bit cren. 16.2.3 setting up 9-bit mode with address detect this mode would typically be used in rs-485 systems. steps to follow when setting up an asynchronous reception with address detect enable: 1. initialize the spbrg register for the appropriate baud rate. if a high speed baud rate is required, set the brgh bit. 2. enable the asynchronous serial port by clearing the sync bit and setting the spen bit. 3. if interrupts are required, set the rcen bit and select the desired priority level with the rcip bit. 4. set the rx9 bit to enable 9-bit reception. 5. set the adden bit to enable address detect. 6. enable reception by setting the cren bit. 7. the rcif bit will be set when reception is com- plete. the interrupt will be acknowledged if the rcie and gie bits are set. 8. read the rcsta register to determine if any error occurred during reception, as well as read bit 9 of data (if applicable). 9. read rcreg to determine if the device is being addressed. 10. if any error occurred, clear the cren bit. 11. if the device has been addressed, clear the adden bit to allow all received data into the receive buffer and interrupt the cpu. figure 16-4: usart receive block diagram x64 baud rate clk spbrg baud rate generator rc7/rx/dt pin buffer and control spen data recovery cren oerr ferr rsr register msb lsb rx9d rcreg register fifo interrupt rcif rcie data bus 8 64 16 or stop start (8) 7 1 0 rx9 ? ? ? note: i/o pins have diode protection to v dd and v ss .
PIC18C601/801 ds39541a-page 186 advance information ? 2001 microchip technology inc. figure 16-5: asynchronous reception table 16-7: registers associated with asynchronous reception start bit bit7/8 bit1 bit0 bit7/8 bit0 stop bit start bit start bit bit7/8 stop bit rx (pin) reg rcv buffer reg rcv shift read rcv buffer reg rcreg rcif (interrupt flag) oerr bit cren word 1 rcreg word 2 rcreg stop bit note: this timing diagram shows three words appearing on the rx input. the rcreg (receive buffer) is read after the third word, causing the oerr (overrun) bit to be set. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 0000 000x 0000 000u pir1 ? adif rcif txif sspif ccp1if tmr2if tmr1if -000 0000 -000 0000 pie1 ? adie rcie txie sspie ccp1ie tmr2ie tmr1ie -000 0000 -000 0000 ipr1 ? adip rcip txip sspip ccp1ip tmr2ip tmr1ip -000 0000 -000 0000 rcsta spen rx9 sren cren ? ferr oerr rx9d 0000 -00x 0000 -00x rcreg usart receive register 0000 0000 0000 0000 txsta csrc tx9 txen sync adden brgh trmt tx9d 0000 0010 0000 0010 spbrg baud rate generator register 0000 0000 0000 0000 legend: x = unknown, - = unimplemented locations read as '0'. shaded cells are not used for asynchronous reception.
? 2001 microchip technology inc. advance information ds39541a-page 187 PIC18C601/801 16.3 usart synchronous master mode in synchronous master mode, the data is transmitted in a half-duplex manner (i.e., transmission and reception do not occur at the same time). when transmitting data, the reception is inhibited and vice versa. synchronous mode is entered by setting bit sync (txsta register). in addition, enable bit spen (rcsta register) is set, in order to configure the rc6/tx/ck and rc7/rx/dt i/o pins to ck (clock) and dt (data) lines, respectively. the master mode indicates that the processor transmits the master clock on the ck line. the master mode is entered by setting bit csrc (txsta register). 16.3.1 usart synchronous master transmission the usart transmitter block diagram is shown in figure 16-1. the heart of the transmitter is the transmit (serial) shift register (tsr). the shift register obtains its data from the read/write transmit buffer register (txreg). the txreg register is loaded with data in software. the tsr register is not loaded until the last bit has been transmitted from the previous load. as soon as the last bit is transmitted, the tsr is loaded with new data from the txreg (if available). once the txreg register transfers the data to the tsr register (occurs in one t cy ), the txreg is empty and interrupt bit txif (pir registers) is set. the interrupt can be enabled/disabled by setting/clearing enable bit txie (pie registers). flag bit txif will be set, regardless of the state of enable bit txie, and cannot be cleared in software. it will reset only when new data is loaded into the txreg register. while flag bit txif indicates the status of the txreg register, another bit trmt (txsta register) shows the status of the tsr register. trmt is a read only bit, which is set when the tsr is empty. no interrupt logic is tied to this bit, so the user has to poll this bit in order to determine if the tsr reg- ister is empty. the tsr is not mapped in data memory, so it is not available to the user. steps to follow when setting up a synchronous master transmission: 1. initialize the spbrg register for the appropriate baud rate (section 16.1). 2. enable the synchronous master serial port by setting bits sync, spen, and csrc. 3. if interrupts are desired, set enable bit txie. 4. if 9-bit transmission is desired, set bit tx9. 5. enable the transmission by setting bit txen. 6. if 9-bit transmission is selected, the ninth bit should be loaded in bit tx9d. 7. start transmission by loading data to the txreg register. table 16-8: registers associated with synchronous master transmission name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 0000 000x 0000 000u pir1 ? adif rcif txif sspif ccp1if tmr2if tmr1if -000 0000 -000 0000 pie1 ? adie rcie txie sspie ccp1ie tmr2ie tmr1ie -000 0000 -000 0000 ipr1 ? adip rcip txip sspip ccp1ip tmr2ip tmr1ip -000 0000 -000 0000 rcsta spen rx9 sren cren ? ferr oerr rx9d 0000 -00x 0000 -00x txreg usart transmit register 0000 0000 0000 0000 txsta csrc tx9 txen sync adden brgh trmt tx9d 0000 0010 0000 0010 spbrg baud rate generator register 0000 0000 0000 0000 legend: x = unknown, - = unimplemented, read as '0'. shaded cells are not used for synchronous master transmission.
PIC18C601/801 ds39541a-page 188 advance information ? 2001 microchip technology inc. figure 16-6: synchronous transmission figure 16-7: synchronous transmission (through txen) bit 0 bit 1 bit 7 word 1 q1 q2 q3q4 q1 q2 q3 q4 q1 q2q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q3q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 bit 2 bit 0 bit 1 bit 7 rc7/rx/dt rc6/tx/ck write to txreg reg txif bit (interrupt flag) trmt txen bit ? 1 ? ? 1 ? note: sync master mode; spbrg = ? 0 ? ; continuous transmission of two 8-bit words. word 2 trmt bit write word 1 write word 2 pin pin rc7/rx/dt pin rc6/tx/ck pin write to txreg reg txif bit trmt bit bit0 bit1 bit2 bit6 bit7 txen bit
? 2001 microchip technology inc. advance information ds39541a-page 189 PIC18C601/801 16.3.2 usart synchronous master reception once synchronous master mode is selected, reception is enabled by setting either enable bit sren (rcsta register), or enable bit cren (rcsta register). data is sampled on the rc7/rx/dt pin on the falling edge of the clock. if enable bit sren is set, only a single word is received. if enable bit cren is set, the reception is continuous until cren is cleared. if both bits are set, then cren takes precedence. when setting up a synchronous master reception, fol- low these steps: 1. initialize the spbrg register for the appropriate baud rate (section 16.1). 2. enable the synchronous master serial port by setting bits sync, spen and csrc. 3. ensure bits cren and sren are clear. 4. if interrupts are desired, set enable bit rcie. 5. if 9-bit reception is desired, set bit rx9. 6. if a single reception is required, set bit sren. for continuous reception, set bit cren. 7. interrupt flag bit rcif will be set when reception is complete and an interrupt will be generated if the enable bit rcie was set. 8. read the rcsta register to get the ninth bit (if enabled) and determine if any error occurred during reception. 9. read the 8-bit received data by reading the rcreg register. 10. if any error occurred, clear the error by clearing bit cren. table 16-9: registers associated with synchronous master reception figure 16-8: synchronous reception (master mode, sren) name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 0000 000x 0000 000u pir1 ? adif rcif txif sspif ccp1if tmr2if tmr1if -000 0000 -000 0000 pie1 ? adie rcie txie sspie ccp1ie tmr2ie tmr1ie -000 0000 -000 0000 ipr1 ? adip rcip txip sspip ccp1ip tmr2ip tmr1ip -000 0000 -000 0000 rcsta spen rx9 sren cren ? ferr oerr rx9d 0000 -00x 0000 -00x rcreg usart receive register 0000 0000 0000 0000 txsta csrc tx9 txen sync adden brgh trmt tx9d 0000 0010 0000 0010 spbrg baud rate generator register 0000 0000 0000 0000 legend: x = unknown, - = unimplemented, read as '0'. shaded cells are not used for synchronous master reception. cren bit rc7/rx/dt pin rc6/tx/ck pin write to bit sren sren bit rcif bit (interrupt) read rxreg note: timing diagram demonstrates sync master mode with bit sren = ? 1 ? and bit brgh = ? 0 ? . q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q2 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4q1 q2 q3 q4 q1 q2 q3 q4 ? 0 ? bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 ? 0 ? q1 q2 q3 q4
PIC18C601/801 ds39541a-page 190 advance information ? 2001 microchip technology inc. 16.4 usart synchronous slave mode synchronous slave mode differs from the master mode, in that the shift clock is supplied externally at the rc6/tx/ck pin (instead of being supplied internally in master mode). this allows the device to transfer or receive data while in sleep mode. slave mode is entered by clearing bit csrc (txsta register). 16.4.1 usart synchronous slave transmit the operation of the synchronous master and slave modes are identical, except in the case of the sleep mode. if two words are written to the txreg and then the sleep instruction is executed, the following will occur: a) the first word will immediately transfer to the tsr register and transmit. b) the second word will remain in txreg register. c) flag bit txif will not be set. d) when the first word has been shifted out of tsr, the txreg register will transfer the second word to the tsr and flag bit txif will be set. e) if enable bit txie is set, the interrupt will wake the chip from sleep. if the global interrupt is enabled, the program will branch to the interrupt vector. when setting up a synchronous slave transmission, follow these steps: 1. enable the synchronous slave serial port by set- ting bits sync and spen and clearing bit csrc. 2. clear bits cren and sren. 3. if interrupts are desired, set enable bit txie. 4. if 9-bit transmission is desired, set bit tx9. 5. enable the transmission by setting enable bit txen. 6. if 9-bit transmission is selected, the ninth bit should be loaded in bit tx9d. 7. start transmission by loading data to the txreg register. 16.4.2 usart synchronous slave reception the operation of the synchronous master and slave modes is identical, except in the case of the sleep mode and bit sren, which is a "don ? t care" in slave mode. if receive is enabled by setting bit cren prior to the sleep instruction, then a word may be received during sleep. on completely receiving the word, the rsr register will transfer the data to the rcreg register, and if enable bit rcie bit is set, the interrupt generated will wake the chip from sleep. if the global interrupt is enabled, the program will branch to the interrupt vector. when setting up a synchronous slave reception, follow these steps: 1. enable the synchronous master serial port by setting bits sync and spen and clearing bit csrc. 2. if interrupts are desired, set enable bit rcie. 3. if 9-bit reception is desired, set bit rx9. 4. to enable reception, set enable bit cren. 5. flag bit rcif will be set when reception is com- plete. an interrupt will be generated if enable bit rcie was set. 6. read the rcsta register to get the ninth bit (if enabled) and determine if any error occurred during reception. 7. read the 8-bit received data by reading the rcreg register. 8. if any error occurred, clear the error by clearing bit cren. table 16-10: registers associated with synchronous slave transmission name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 0000 000x 0000 000u pir1 ? adif rcif txif sspif ccp1if tmr2if tmr1if -000 0000 -000 0000 pie1 ? adie rcie txie sspie ccp1ie tmr2ie tmr1ie -000 0000 -000 0000 ipr1 ? adip rcip txip sspip ccp1ip tmr2ip tmr1ip -000 0000 -000 0000 rcsta spen rx9 sren cren ? ferr oerr rx9d 0000 -00x 0000 -00x txreg usart transmit register 0000 0000 0000 0000 txsta csrc tx9 txen sync adden brgh trmt tx9d 0000 0010 0000 0010 spbrg baud rate generator register 0000 0000 0000 0000 legend: x = unknown, - = unimplemented, read as '0'. shaded cells are not used for synchronous slave transmission.
? 2001 microchip technology inc. advance information ds39541a-page 191 PIC18C601/801 table 16-11: registers associated with synchronous slave reception name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 0000 000x 0000 000u pir1 ? adif rcif txif sspif ccp1if tmr2if tmr1if -000 0000 -000 0000 pie1 ? adie rcie txie sspie ccp1ie tmr2ie tmr1ie -000 0000 -000 0000 ipr1 ? adip rcip txip sspip ccp1ip tmr2ip tmr1ip -000 0000 -000 0000 rcsta spen rx9 sren cren ? ferr oerr rx9d 0000 -00x 0000 -00x rcreg usart receive register 0000 0000 0000 0000 txsta csrc tx9 txen sync adden brgh trmt tx9d 0000 0010 0000 0010 spbrg baud rate generator register 0000 0000 0000 0000 legend: x = unknown, - = unimplemented, read as '0'. shaded cells are not used for synchronous slave reception.
PIC18C601/801 ds39541a-page 192 advance information ? 2001 microchip technology inc. notes:
? 2001 microchip technology inc. advance information ds39541a-page 193 PIC18C601/801 17.0 10-bit analog-to-digital converter (a/d) module the analog-to-digital (a/d) converter module has 8 inputs for the PIC18C601 devices and 12 for the pic18c801 devices. this module has the adcon0, adcon1, and adcon2 registers. the a/d allows conversion of an analog input signal to a corresponding 10-bit digital number. the a/d module has five registers: a/d result high register (adresh) a/d result low register (adresl) a/d control register 0 (adcon0) a/d control register 1 (adcon1) a/d control register 2 (adcon2) the adcon0 register, shown in register 17-1, controls the operation of the a/d module. the adcon1 register, shown in register 17-2, configures the functions of the port pins. the adcon2, shown in register 16-3, config- ures the a/d clock source and justification. register 17-1: adcon0 register u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? chs3 chs2 chs1 chs0 go/done adon bit 7 bit 0 bit 7-6 unimplemented: read as '0' bit 5-2 chs3:chs0: analog channel select bits 0000 = channel 00, (an0) 0001 = channel 01, (an1) 0010 = channel 02, (an2) 0011 = channel 03, (an3) 0100 = channel 04, (an4) 0101 = channel 05, (an5) 0110 = channel 06, (an6) 0111 = channel 07, (an7) 1000 = channel 08, (an8) (1) 1001 = channel 09, (an9) (1) 1010 = channel 10, (an10) (1) 1011 = channel 11, (an11) (1) 1100 = reserved 1101 = reserved 1110 = reserved 1111 = reserved these channels are not available on the PIC18C601 devices. bit 1 go/done : a/d conversion status bit when adon = 1: 1 = a/d conversion in progress. setting this bit starts an a/d conversion cycle. this bit is automatically cleared by hardware when the a/d conversion is complete. 0 = a/d conversion not in progress bit 0 adon: a/d on bit 1 = a/d converter module is operating 0 = a/d converter module is shut-off and consumes no operating current legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown
PIC18C601/801 ds39541a-page 194 advance information ? 2001 microchip technology inc. register 17-2: adcon1 register u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? vcfg1 vcfg0 pcfg3 pcfg2 pcfg1 pcfg0 bit 7 bit 0 bit 7-6 unimplemented: read as '0' bit 5-4 vcfg1:vcfg0: voltage reference configuration bits bit 3-0 pcfg3:pcfg0: a/d port configuration control bits legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown a/d v ref + a/d v ref - 00 a vdd a vss 01 external v ref +a vss 10 a vdd external v ref - 11 external v ref + external v ref - a = analog input d = digital i/o shaded cells = additional a/d channels available on pic18c801 devices. an11 an10 an9 an8 an7 an6 an5 an4 an3 an2 an1 an0 0000 a a a a a a a a aaaa 0001 a a a a a a a a aaaa 0010 a a a a a a a a aaaa 0011 a a a a a a a a aaaa 0100 d a a a a a a a aaaa 0101 d d a a a a a a aaaa 0110 d d d a a a a a aaaa 0111 d d d d a a a a aaaa 1000 d d d d d a a a aaaa 1001 d d d dddaaaaaa 1010 d d d ddddaaaaa 1011 d d d d d d d daaaa 1100 d d d ddddddaaa 1101 d d d dddddddaa 1110 d d d dddddddda 1111 d d d d d d d d dddd
? 2001 microchip technology inc. advance information ds39541a-page 195 PIC18C601/801 register 17-3: adcon2 register the analog reference voltage is software selectable to either the device ? s positive and negative supply voltage (v dd and v ss ), or the voltage level on the ra3/an3/v ref + pin and ra2/an2/v ref -. the a/d converter has a unique feature of being able to operate while the device is in sleep mode. to oper- ate in sleep, the a/d conversion clock must be derived from the a/d ? s internal rc oscillator. the output of the sample and hold is the input into the converter, which generates the result via successive approximation. a device reset forces all registers to their reset state. this forces the a/d module to be turned off and any conversion is aborted. each port pin associated with the a/d converter can be configured as an analog input (ra3 can also be a voltage reference), or as a digital i/o. the adresh and adresl registers contain the result of the a/d conversion. when the a/d conver- sion is complete, the result is loaded into the adresh/adresl registers, the go/done bit (adcon0 register) is cleared, and a/d interrupt flag bit adif is set. the block diagram of the a/d module is shown in figure 17-1. r/w-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 adfm ? ? ? ? adcs2 adcs1 adcs0 bit 7 bit 0 bit 7 adfm: a/d result format select bit 1 = right justified 0 = left justified bit 6-3 unimplemented: read as '0' bit 2-0 adcs2:adcs0: a/d conversion clock select bits 000 = f osc /2 001 = f osc /8 010 = f osc /32 011 = f rc (clock derived from an internal rc oscillator = 1 mhz max) 100 = f osc /4 101 = f osc /16 110 = f osc /64 111 = f rc (clock derived from an internal rc oscillator = 1 mhz max) legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown
PIC18C601/801 ds39541a-page 196 advance information ? 2001 microchip technology inc. figure 17-1: a/d block diagram (input voltage) v in v ref + (reference voltage) av dd vcfg0 chs3:chs0 rf2/an7 rf1/an6 rf0/an5 ra5/an4 ra3/an3/v ref + ra2/an2/v ref - ra1/an1 ra0/an0 0111 0110 0101 0100 0011 0010 0001 0000 a/d converter v ref - (reference voltage) av ss vcfg1 rh7/an11 (1) rh6/an10 (1) rh5/an9 (1) rh4/an8 (1) 1010 1001 1000 1011 note 1: these channels are not available on the PIC18C601 devices.
? 2001 microchip technology inc. advance information ds39541a-page 197 PIC18C601/801 the value in the adresh/adresl registers is not modified for a power-on reset. the adresh/adresl registers will contain unknown data after a power-on reset. after the a/d module has been configured as desired, the selected channel must be acquired before the con- version is started. the analog input channels must have their corresponding tris bits selected as an input. to determine acquisition time, see section 17.1. after this acquisition time has elapsed, the a/d conver- sion can be started. the following steps should be fol- lowed to do an a/d conversion: 1. configure the a/d module: configure analog pins, voltage reference and digital i/o (adcon1) select a/d input channel (adcon0) select a/d conversion clock (adcon2) turn on a/d module (adcon0) 2. configure a/d interrupt (if desired): clear adif bit set adie bit set gie bit 3. wait the required acquisition time. 4. start conversion: set go/done bit (adcon0 register) 5. wait for a/d conversion to complete, by either: polling for the go/done bit to be cleared, or waiting for the a/d interrupt 6. read a/d result registers (adresh:adresl); clear bit adif, if required. 7. for next conversion, go to step 1 or step 2, as required. the a/d conversion time per bit is defined as t ad . a minimum wait of 2t ad is required before next acquisition starts. figure 17-2: analog input model v ain c pin rs anx 5 pf v dd v t = 0.6 v v t = 0.6 v i leakage r ic 1 k sampling switch ss r ss c hold = 120 pf v ss 6v sampling switch 5v 4v 3v 2v 567891011 ( k ? ) v dd 500 na legend: c pin v t i leakage r ic ss c hold = input capacitance = threshold voltage = leakage current at the pin due to = interconnect resistance = sampling switch = sample/hold capacitance (from dac) various junctions = sampling switch resistance r ss
PIC18C601/801 ds39541a-page 198 advance information ? 2001 microchip technology inc. 17.1 a/d acquisition requirements for the a/d converter to meet its specified accuracy, the charge holding capacitor (c hold ) must be allowed to fully charge to the input channel voltage level. the analog input model is shown in figure 17-2. the source impedance (r s ) and the internal sampling switch (r ss ) impedance directly affect the time required to charge the capacitor c hold . the sampling switch (r ss ) impedance varies over the device voltage (v dd ). the source impedance affects the offset voltage at the analog input (due to pin leakage current). the maximum recommended impedance for analog sources is 2.5k ? . after the analog input channel is selected (changed), this acquisition must be done before the conversion can be started. to calculate the minimum acquisition time, equation 17-1 may be used. this equation assumes that 1/2 lsb error is used (1024 steps for the a/d). the 1/2 lsb error is the maximum error allowed for the a/d to meet its specified resolution. example 17-1 shows the calculation of the minimum required acquisition time t acq . this calculation is based on the following application system assumptions: c hold = 120 pf rs = 2.5 k ? conversion error 1/2 lsb v dd = 5v rss = 7 k ? temperature = 50 c (system max.) v hold =0v @ time = 0 equation 17-1: acquisition time equation 17-2: a/d minimum charging time example 17-1: calculating the minimum required acquisition time note: when the conversion is started, the hold- ing capacitor is disconnected from the input pin. t acq = amplifier settling time + holding capacitor charging time + temperature coefficient =t amp + t c + t coff v hold = (v ref - (v ref /2048)) (1 - e (-tc/c hold (r ic + r ss + r s )) ) or t c = -(120 pf)(1 k ? + r ss + r s ) ln(1/2047) t acq =t amp + t c + t coff temperature coefficient is only required for temperatures > 25 c. t acq =2 s + t c + [(temp - 25 c)(0.05 s/ c)] t c =-c hold (r ic + r ss + r s ) ln(1/2047) -120 pf (1 k ? + 7 k ? + 2.5 k ? ) ln(0.0004885) -120 pf (10.5 k ? ) ln(0.0004885) -1.26 s (-7.6241) 9.61 s t acq =2 s + 9.61 s + [(50 c - 25 c)(0.05 s/ c)] 11.61 s + 1.25 s 12.86 s
? 2001 microchip technology inc. advance information ds39541a-page 199 PIC18C601/801 17.2 selecting the a/d conversion clock the a/d conversion time per bit is defined as t ad . the a/d conversion requires 12 t ad per 10-bit conversion. the source of the a/d conversion clock is software selectable. there are seven possible options for t ad : 2t osc 4t osc 8t osc 16t osc 32t osc 64t osc internal rc oscillator for correct a/d conversions, the a/d conversion clock (t ad ) must be selected to ensure a minimum t ad time of 1.6 s. table 17-1 shows the resultant t ad times derived from the device operating frequencies and the a/d clock source selected. 17.3 configuring analog port pins the adcon1, trisa, trisf and trish registers control the operation of the a/d port pins. the port pins needed as analog inputs must have their correspond- ing tris bits set (input). if the tris bit is cleared (out- put), the digital output level (v oh or v ol ) will be converted. the a/d operation is independent of the state of the chs3:chs0 bits and the tris bits. table 17-1: t ad vs. device operating frequencies note 1: when reading the port register, all pins configured as analog input channels will read as cleared (a low level). pins config- ured as digital inputs will convert an ana- log input. analog levels on a digitally configured input will not affect the conver- sion accuracy. 2: analog levels on any pin defined as a dig- ital input may cause the input buffer to consume current out of the device ? s spec- ification limits. ad clock source (t ad ) maximum device frequency operation adcs2:adcs0 PIC18C601/801 pic18lc601/801 (5) 2t osc 000 1.25 mhz 666 khz 4t osc 100 2.50 mhz 1.33 mhz 8t osc 001 5.00 mhz 2.67 mhz 16t osc 101 10.0 mhz 5.33 mhz 32t osc 010 20.0 mhz 10.67 mhz 64t osc 110 ?? rc x11 ?? note 1: the rc source has a typical t ad time of 4 s. 2: these values violate the minimum required t ad time. 3: for faster conversion times, the selection of another clock source is recommended. 4: for device frequencies above 1 mhz, the device must be in sleep for the entire conversion or the a/d accuracy may be out of specification. 5: this column is for the lc devices only.
PIC18C601/801 ds39541a-page 200 advance information ? 2001 microchip technology inc. 17.4 a/d conversions figure 17-3 shows the operation of the a/d converter after the go bit has been set. clearing the go/done bit during a conversion will abort the current conver- sion. the a/d result register pair will not be updated with the partially completed a/d conversion sample. that is, the adresh:adresl registers will continue to contain the value of the last completed conversion (or the last value written to the adresh:adresl reg- isters). after the a/d conversion is aborted, a 2t ad wait is required before the next acquisition is started. after this 2t ad wait, acquisition on the selected channel is automatically started. 17.5 use of the ccp2 trigger an a/d conversion can be started by the ? special event trigger ? of the ccp2 module. this requires that the ccp2m3:ccp2m0 bits (ccp2con<3:0>) be pro- grammed as 1011 , and that the a/d module is enabled (adon bit is set). when the trigger occurs, the go/done bit will be set, starting the a/d conversion and the timer1 (or timer3) counter will be reset to zero. timer1 (or timer3) is reset to automatically repeat the a/d acquisi- tion period with minimal software overhead (moving adresh/adresl to the desired location). the appropri- ate analog input channel must be selected and the mini- mum acquisition done before the ? special event trigger ? sets the go/done bit (starts a conversion). if the a/d module is not enabled (adon is cleared), the ? special event trigger ? will be ignored by the a/d mod- ule, but will still reset the timer1 (or timer3) counter. figure 17-3: a/d conversion t ad cycles note: the go/done bit should not be set in the same instruction that turns on the a/d. t ad 1 t ad 2 t ad 3 t ad 4 t ad 5 t ad 6 t ad 7 t ad 8 t ad 11 set go bit holding capacitor is disconnected from analog input (typically 100 ns) b9 b9 b8 b7 b6 b5 b4 b3 t ad 9 t ad 10 b2 b1 t cy - t ad next q4: adresh/adresl is loaded, go bit is cleared, adif bit is set, holding capacitor is connected to analog input. conversion starts b0
? 2001 microchip technology inc. advance information ds39541a-page 201 PIC18C601/801 table 17-2: summary of a/d registers name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 0000 000x 0000 000u pir1 ? adif rcif txif sspif ccp1if tmr2if tmr1if -000 0000 -000 0000 pie1 ? adie rcie txie sspie ccp1ie tmr2ie tmr1ie -000 0000 -000 0000 ipr1 ? adip rcip txip sspip ccp1ip tmr2ip tmr1ip -000 0000 -000 0000 pir2 ? ? ? ? bclif lvdif tmr3if ccp2if -0-- 0000 -0-- 0000 pie2 ? ? ? ? bclie lvdie tmr3ie ccp2ie ---- 0000 ---- 0000 ipr2 ? ? ? ? bclip lvdip tmr3ip ccp2ip ---- 0000 ---- 0000 adresh a/d result register xxxx xxxx uuuu uuuu adresl a/d result register xxxx xxxx uuuu uuuu adcon0 ? ? chs3 chs3 chs1 chs0 go/done adon 0000 00-0 0000 00-0 adcon1 ? ? vcfg1 vcfg0 pcfg3 pcfg2 pcfg1 pcfg0 ---- -000 ---- -000 adcon2 adfm ? ? ? ? adcs2 adcs1 adcs0 0--- -000 0--- -000 porta ? ? ra5 ra4 ra3 ra2 ra1 ra0 --0x 0000 --0u 0000 trisa ? porta data direction register --11 1111 --11 1111 portf rf7 rf6 rf5 rf4 rf3 rf2 rf1 rf0 x000 0000 u000 0000 latf latf7 latf6 latf5 latf4 latf3 latf2 latf1 latf0 xxxx xxxx uuuu uuuu trisf portf data direction control register 1111 1111 1111 1111 porth (1) rh7 rh6 rh5 rh4 rh3 rh2 rh1 rh0 0000 xxxx 0000 xxxx lath (1) lath7 lath6 lath5 lath4 lath3 lath2 lath1 lath0 xxxx xxxx uuuu uuuu trish (1) porth data direction control register 1111 1111 1111 1111 legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. shaded cells are not used for a/d conversion. note 1: only available on pic18c801 devices.
PIC18C601/801 ds39541a-page 202 advance information ? 2001 microchip technology inc. notes:
? 2001 microchip technology inc. advance information ds39541a-page 203 PIC18C601/801 18.0 low voltage detect in many applications, the ability to determine if the device voltage (v dd ) is below a specified voltage level is a desirable feature. a window of operation for the application can be created, where the application soft- ware can do "housekeeping tasks", before the device voltage exits the valid operating range. this can be done using the low voltage detect module. this module is software programmable circuitry, where a device voltage trip point can be specified (internal ref- erence voltage or external voltage input). when the voltage of the device becomes lower than the specified point, an interrupt flag is set. if the interrupt is enabled, the program execution will branch to the interrupt vec- tor address and the software can then respond to that interrupt source. the low voltage detect circuitry is completely under software control. this allows the circuitry to be "turned off" by the software, which minimizes the current con- sumption for the device. figure 18-1 shows a possible application voltage curve (typically for batteries). over time, the device voltage decreases. when the device voltage equals voltage v a , the lvd logic generates an interrupt. this occurs at time t a . the application software then has the time, until the device voltage is no longer in valid operating range, to shut-down the system. voltage point v b is the minimum valid operating voltage specification. this occurs at time t b . t b - t a is the total time for shut-down. figure 18-1: typical low voltage detect application figure 18-2 shows the block diagram for the lvd mod- ule. a comparator uses an internally generated refer- ence voltage as the set point. when the selected tap output of the device voltage crosses the set point (is lower than), the lvdif bit (pir registers) is set. each node in the resister divider represents a ? trip point ? voltage. the ? trip point ? voltage is the minimum supply voltage level at which the device can operate, before the lvd module asserts an interrupt. when the supply voltage is equal to the trip point, the voltage tapped off of the resistor array (or external lvdin input pin) is equal to the voltage generated by the internal voltage reference module. the comparator then gener- ates an interrupt signal setting the lvdif bit. this volt- age is software programmable to any one of 16 values (see figure 18-2). the trip point is selected by programming the lvdl3:lvdl0 bits (lvdcon<3:0>). figure 18-2: low voltage detect (lvd) block diagram time voltage v a v b t a t b v a = lvd trip point v b = minimum valid device operating range legend: lvdif v dd 16 to 1 mux lvden lvd control register internally generated reference voltage lvdin
PIC18C601/801 ds39541a-page 204 advance information ? 2001 microchip technology inc. 18.1 control register the low voltage detect control register (register 18-1) controls the operation of the low voltage detect circuitry. register 18-1: lvdcon register u-0 u-0 r-0 r/w-0 r/w-0 r/w-1 r/w-0 r/w-1 ? ? irvst lvden lvdl3 lvdl2 lvdl1 lvdl0 bit 7 bit 0 bit 7-6 unimplemented: read as '0' bit 5 irvst: internal reference voltage stable flag bit 1 = indicates that the low voltage detect logic will generate the interrupt flag at the specified voltage range 0 = indicates that the low voltage detect logic will not generate the interrupt flag at the specified voltage range and the lvd interrupt should not be enabled bit 4 lvden: low voltage detect power enable bit 1 = enables lvd, powers up lvd circuit 0 = disables lvd, powers down lvd circuit bit 3-0 lvdl3:lvdl0: low voltage detection limit bits 1111 = external analog input is used (input comes from the lvdin pin) 1110 = 4.5v 1101 = 4.2v 1100 = 4.0v - reserved on PIC18C601/801 1011 = 3.8v - reserved on PIC18C601/801 1010 = 3.6v - reserved on PIC18C601/801 1001 = 3.5v - reserved on PIC18C601/801 1000 = 3.3v - reserved on PIC18C601/801 0111 = 3.0v - reserved on PIC18C601/801 0110 = 2.8v - reserved on PIC18C601/801 0101 = 2.7v - reserved on PIC18C601/801 0100 = 2.5v - reserved on PIC18C601/801 0011 = 2.4v - reserved on PIC18C601/801 0010 = 2.2v - reserved on PIC18C601/801 0001 = 2.0v - reserved on PIC18C601/801 0000 = reserved on PIC18C601/801 and pic18lc801/601 lvdl3:lvdl0 modes which result in a trip point below the valid operating voltage of the device are not tested. legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown
? 2001 microchip technology inc. advance information ds39541a-page 205 PIC18C601/801 18.2 operation depending on the power source for the device voltage, the voltage normally decreases relatively slowly. this means that the lvd module does not need to be con- stantly operating. to decrease current consumption, the lvd circuitry only needs to be enabled for short periods, where the voltage is checked. after doing the check, the lvd module may be disabled. each time that the lvd module is enabled, the circuitry requires some time to stabilize. after the circuitry has stabilized, all status flags may be cleared. the module will then indicate the proper state of the system. the following steps are needed to setup the lvd module: 1. write the value to the lvdl3:lvdl0 bits (lvdcon register), which selects the desired lvd trip point. 2. ensure that lvd interrupts are disabled (the lvdie bit is cleared or the gie bit is cleared). 3. enable the lvd module (set the lvden bit in the lvdcon register). 4. wait for the lvd module to stabilize (the irvst bit to become set). 5. clear the lvd interrupt flag, which may have falsely become set, until the lvd module has stabilized (clear the lvdif bit). 6. enable the lvd interrupt (set the lvdie and the gie bits). figure 18-3 shows typical waveforms that the lvd module may be used to detect. figure 18-3: low voltage detect waveforms v lvd v dd lvdif v lvd v dd enable lvd internally generated 50 ms lvdif may not be set enable lvd 50 ms lvdif lvdif cleared in software lvdif cleared in software lvdif cleared in software, case 1: case 2: lvdif remains set since lvd condition still exists reference stable internally generated reference stable
PIC18C601/801 ds39541a-page 206 advance information ? 2001 microchip technology inc. 18.2.1 reference voltage set point the internal reference voltage of the lvd module may be used by other internal circuitry (the programmable brown-out reset). if these circuits are disabled (lower current consumption), the reference voltage circuit requires time to become stable before a low voltage con- dition can be reliably detected. this time is invariant of system clock speed. this start-up time is specified in electrical specification parameter #36. the low voltage interrupt flag will not be enabled until a stable reference voltage is reached. refer to the waveform in figure 18-3. 18.2.2 current consumption when the module is enabled, the lvd comparator and voltage divider are enabled and will consume static cur- rent. the voltage divider can be tapped from multiple places in the resistor array. total current consumption, when enabled, is specified in electrical specification parameter #d022b. 18.3 external analog voltage input the lvd module has an additional feature that allows the user to supply the trip point voltage to the module from an external source (the lvdin pin). the lvdin pin is used as the trip point when the lvdl3:lvdl0 bits equal ? 1111 ? . this state connects the lvdin pin volt- age to the comparator. the other comparator input is connected to an internal reference voltage source. 18.4 operation during sleep when enabled, the lvd circuitry continues to operate during sleep. if the device voltage crosses the trip point, the lvdif bit will be set and the device will wake- up from sleep. device execution will continue from the interrupt vector address, if interrupts have been globally enabled. 18.5 effects of a reset a device reset forces all registers to their reset state. this forces the lvd module to be turned off.
? 2001 microchip technology inc. advance information ds39541a-page 207 PIC18C601/801 19.0 special features of the cpu there are several features intended to maximize system reliability, minimize cost through elimination of external components and provide power saving operating modes: osc selection reset - power-on reset (por) - power-up timer (pwrt) - oscillator start-up timer (ost) interrupts watchdog timer (wdt) sleep id locations PIC18C601/801 devices have a watchdog timer, which can be permanently enabled/disabled via the configuration bits, or it can be software controlled. by default, the watchdog timer is disabled to allow soft- ware control. it runs off its own rc oscillator for cost reduction. there are two timers that offer necessary delays on power-up. one is the oscillator start-up timer (ost), intended to keep the chip in reset until the crystal oscillator is stable. the other is the power- up timer (pwrt), which provides a fixed delay on power-up only, designed to keep the part in reset while the power supply stabilizes. with these two tim- ers on-chip, most applications need no external reset circuitry. sleep mode is designed to offer a very low current power-down mode. the user can wake-up from sleep through external reset, watchdog timer wake-up or through an interrupt. several oscillator options are also available to allow the part to fit the application. the rc oscillator option saves system cost, while the lp crystal option saves power. by default, hs oscillator mode is selected. there are two main modes of operations for external memory inter- face: 8-bit and 16-bit (default). a set of configuration bits are used to select various options. 19.1 configuration bits the configuration bits can be programmed (read as ? 0 ? ), or left unprogrammed (read as ? 1 ? ), to select various device configurations. these bits are mapped starting at program memory location 300000h. the user will note that address 300000h is beyond the user program memory space. in fact, it belongs to the configuration memory space (300000h - 3fffffh), which can only be accessed using table reads and table writes. table 19-1: configuration bits and device ids file name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default/ unprogrammed value 300001h config1h ? ? ? ? ? ? fosc1 fosc0 ---- --11 300002h config2l ? bw ? ? ? ? ? pwrten -1-- ---1 300003h config2h ? ? ? ? wdtps2 wdtps1 wdtps0 wdten ---- 1110 300006h config4l r ? ? ? ? ? ? stvren 1--- ---1 3ffffeh devid1 dev2 dev1 dev0 rev4 rev3 rev2 rev1 rev0 0000 0000 3fffffh devid2 dev10 dev9 dev8 dev7 dev6 dev5 dev4 dev3 0000 0000 legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition, r = reserved, maintain ? 1 ? . shaded cells are unimplemented, read as ? 0 ? .
PIC18C601/801 ds39541a-page 208 advance information ? 2001 microchip technology inc. register 19-1: configuration register 1 high (config1h: byte address 0300001h) register 19-2: configuration register 2 low (config2l: byte address 300002h) u-0 u-0 u-0 u-0 u-0 u-0 r/p-1 r/p-1 ? ? ? ? ? ? fosc1 fosc0 bit 7 bit 0 bit 7-2 unimplemented: read as ? 0 ? bit 2-0 fosc1:fosc0 : oscillator selection bits 11 = rc oscillator 10 = hs oscillator 01 = ec oscillator 00 = lp oscillator legend: r = reserved r = readable bit p = programmable bit u = unimplemented bit, read as ? 0 ? - n = value when device is unprogrammed u = unchanged from programmed state u-0 r/p-1 u-0 u-0 u-0 u-0 u-0 r/p-1 ? bw ? ? ? ? ? pwrten bit 7 bit 0 bit 7 unimplemented: read as ? 0 ? bit 6 bw: external bus data width bit 1 = 16-bit external bus mode 0 = 8-bit external bus mode bit 5-1 unimplemented: read as ? 0 ? bit 0 pwrten : power-up timer enable bit 1 = pwrt disabled 0 = pwrt enabled legend: r = reserved r = readable bit p = programmable bit u = unimplemented bit, read as ? 0 ? - n = value when device is unprogrammed u = unchanged from programmed state
? 2001 microchip technology inc. advance information ds39541a-page 209 PIC18C601/801 register 19-3: configuration register 2 high (config2h: byte address 300003h) register 19-4: configuration register 4 low (config4l: byte address 300006h) u-0 u-0 u-0 u-0 r/p-1 r/p-1 r/p-1 r/p-1 ? ? ? ? wdtps2 wdtps1 wdtps0 wdten bit 7 bit 0 bit 7-4 unimplemented: read as ? 0 ? bit 3-1 wdtps2:wdtps0: watchdog timer postscale select bits 000 =1:128 001 =1:64 010 =1:32 011 =1:16 100 =1:8 101 =1:4 110 =1:2 111 =1:1 bit 0 wdten: watchdog timer enable bit 1 = wdt enabled 0 = wdt disabled (control is placed on the swdten bit) legend: r = reserved r = readable bit p = programmable bit u = unimplemented bit, read as ? 0 ? - n = value when device is unprogrammed u = unchanged from programmed state r/p-1 u-0 u-0 u-0 u-0 u-0 r/p-1 r/p-1 r ? ? ? ? ? ? stvren bit 7 bit 0 bit 7 reserved: maintain as ? 1 ? bit 6-1 unimplemented: read as ? 0 ? bit 0 stvren: stack full/underflow reset enable bit 1 = stack full/underflow will cause reset 0 = stack full/underflow will not cause reset legend: r = reserved r = readable bit p = programmable bit u = unimplemented bit, read as ? 0 ? - n = value when device is unprogrammed u = unchanged from programmed state
PIC18C601/801 ds39541a-page 210 advance information ? 2001 microchip technology inc. 19.2 watchdog timer (wdt) the watchdog timer is a free running on-chip rc oscil- lator, which does not require any external components. this rc oscillator is separate from the rc oscillator of the osc1/clki pin. that means that the wdt will run, even if the clock on the osc1/clki and osc2/clko pins of the device has been stopped; for example, by execution of a sleep instruction. during normal operation, a wdt time-out generates a device reset (watchdog timer reset). if the device is in sleep mode, a wdt time-out causes the device to wake-up and continue with normal operation (watch- dog timer wake-up). the to bit in the rcon register will be cleared upon a wdt time-out. by default, the watchdog timer is disabled by configu- ration to allow software control over watchdog timer operation. if the wdt is enabled by configuration, soft- ware execution may not disable this function. when the watchdog timer is disabled by configuration, the swdten bit in the wdtcon register enables/ disables the operation of the wdt. the wdt time-out period values may be found in the electrical specifications section under parameter #31. values for the wdt postscaler may be assigned by using configuration bits wdps<3:1> in config2h register. if the watchdog timer is disabled by configu- ration, values for the wdt postscaler may be assigned using the swdps bits in the wdtcon register. 19.2.1 control register register 19-5 shows the wdtcon register. this is a readable and writable register. it contains control bits to control the watchdog timer from user software. if the watchdog timer is enabled by configuration, this regis- ter setting is ignored. register 19-5: wdtcon register note 1: the clrwdt and sleep instructions clear the wdt and the postscaler, if assigned to the wdt, and prevent it from timing out and generating a device reset condition. 2: when a clrwdt instruction is executed and the prescaler is assigned to the wdt, the prescaler count will be cleared, but the prescaler assignment is not changed. u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? ? swdps2 swdps1 swdps0 swdten bit 7 bit 0 bit 7-4 unimplemented : read as ? 0 ? bit 3-1 swdps2:swdps0: software watchdog timer postscale select bits 111 = 1:128 110 = 1:64 101 = 1:32 100 = 1:16 011 = 1:8 010 = 1:4 001 = 1:2 000 = 1:1 bit 0 swdten: software controlled watchdog timer enable bit 1 = watchdog timer is on 0 = watchdog timer is turned off if it is not disabled legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown
? 2001 microchip technology inc. advance information ds39541a-page 211 PIC18C601/801 19.2.2 wdt postscaler the wdt has a postscaler that can extend the wdt reset period. the postscaler may be programmed by the user software or is selected by configuration bits wdtps<2:0> in the config2h register. if the device has the watchdog timer enabled by configuration bits, the device will use predefined set postscaler value. if the device has the watchdog timer disabled by config- uration bits, user software can set desired postscaler value. when the device has the watchdog timer enabled by configuration bits, by default, watchdog postscaler of 1:128 is selected. figure 19-1: watchdog timer block diagram table 19-2: summary of watchdog timer registers postscaler wdt timer 8 - to - 1 mux wdtps2:wdtps0 wdt time-out 8 swdten bit note: wdps2:wdps0 are bits in a configuration register. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 config2h ? ? ? ? wdtps2 wdtps1 wdtps0 wdten rcon ipen r ? ri to pd por r wdtcon ? ? ? ? swdps2 swdps1 swdps0 swdten legend: shaded cells are not used by the watchdog timer.
PIC18C601/801 ds39541a-page 212 advance information ? 2001 microchip technology inc. 19.3 power-down mode (sleep) power-down mode is entered by executing a sleep instruction. upon entering into power-down mode, the following actions are performed: 1. watchdog timer is cleared and kept running. 2. pd bit in rcon register is cleared. 3. to bit in rcon register is set. 4. oscillator driver is turned off. 5. i/o ports maintain the status they had before the sleep instruction was executed. to achieve lowest current consumption, follow these steps before switching to power-down mode: 1. place all i/o pins at either v dd or v ss and ensure no external circuitry is drawing current from i/o pin. 2. power-down a/d and external clocks. 3. pull all hi-impedance inputs to high or low, externally. 4. place t0cki at v ss or v dd . 5. current consumption by portb on-chip pull- ups should be taken into account and disabled, if necessary. the mclr pin must be at a logic high level (v ihmc ). 19.3.1 wake-up from sleep the device can wake-up from sleep through one of the following events: 1. external reset input on mclr pin. 2. watchdog timer wake-up (if wdt was enabled). 3. interrupt from int pin, rb port change, or a peripheral interrupt. the following peripheral interrupts can wake the device from sleep: 4. tmr1 interrupt. timer1 must be operating as an asynchronous counter. 5. tmr3 interrupt. timer3 must be operating as an asynchronous counter. 6. ccp capture mode interrupt. 7. special event trigger (timer1 in asynchronous mode using an external clock). 8. mssp (start/stop) bit detect interrupt. 9. mssp transmit or receive in slave mode (spi/i 2 c). 10. usart rx or tx (synchronous slave mode). 11. a/d conversion (when a/d clock source is rc). other peripherals cannot generate interrupts, since during sleep, no on-chip clocks are present. external mclr reset will cause a device reset. all other events are considered a continuation of program execution and will cause a "wake-up". the to and pd bits in the rcon register can be used to determine the cause of the device reset. the pd bit, which is set on power-up, is cleared when sleep is invoked. the to bit is cleared, if a wdt time-out occurred (and caused wake-up). when the sleep instruction is being executed, the next instruction (pc + 2) is pre-fetched. for the device to wake-up through an interrupt event, the corresponding interrupt enable bit must be set (enabled). wake-up is regardless of the state of the gie bit. if the gie bit is clear (disabled), the device continues execution at the instruction after the sleep instruction. if the gie bit is set (enabled), the device executes the instruction after the sleep instruction and then branches to the inter- rupt address. in cases where the execution of the instruction following sleep is not desirable, the user should have a nop after the sleep instruction. 19.3.2 wake-up using interrupts when global interrupts are disabled (gie cleared) and any interrupt source has both its interrupt enable bit and interrupt flag bit set, one of the following will occur: if an interrupt condition (interrupt flag bit and inter- rupt enable bits are set) occurs before the execu- tion of a sleep instruction, the sleep instruction will complete as a nop . therefore, the wdt and wdt postscaler will not be cleared, the to bit will not be set and pd bits will not be cleared. if the interrupt condition occurs during or after the execution of a sleep instruction, the device will immediately wake-up from sleep. the sleep instruction will be completely executed before the wake-up. therefore, the wdt and wdt postscaler will be cleared, the to bit will be set and the pd bit will be cleared. even if the flag bits were checked before executing a sleep instruction, it may be possible for flag bits to become set before the sleep instruction completes. to determine whether a sleep instruction executed, test the pd bit. if the pd bit is set, the sleep instruction was executed as a nop . to ensure that the wdt is cleared, a clrwdt instruc- tion should be executed before a sleep instruction.
? 2001 microchip technology inc. advance information ds39541a-page 213 PIC18C601/801 figure 19-2: wake-up from sleep through interrupt (1,2) q1 q2 q3 q4 q1 q2 q3 q4 q1 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 osc1 clkout (4) int pin intif bit gieh bit instruction flow pc instruction fetched instruction executed pc pc+2 pc+4 inst(pc) = sleep inst(pc - 1) inst(pc + 2) sleep processor in sleep interrupt latency (3) inst(pc + 4) inst(pc + 2) inst(0008h) inst(000ah) inst(0008h) dummy cycle pc + 4 0008h 000ah dummy cycle t ost (2) pc+4 note 1: hs or lp oscillator mode assumed. 2: gie set is assumed. in this case, after wake- up, the processor jumps to the interrupt routine. if gie is cleared, execution will continue in-line. 3: t ost = 1024t osc (drawing not to scale). this delay will not occur for rc and ec osc modes. 4: clkout is not available in these oscillator modes, but shown here for timing reference.
PIC18C601/801 ds39541a-page 214 advance information ? 2001 microchip technology inc. notes:
? 2001 microchip technology inc. advance information ds39541a-page 215 PIC18C601/801 20.0 instruction set summary the PIC18C601/801 instruction set adds many enhancements to the previous picmicro ? instruction sets, while maintaining an easy migration path from them. with few exceptions, instructions are a single program memory word (16-bits). each single word instruction is divided into an opcode, which specifies the instruc- tion type, and one or more operands which further specify the operation of the instruction. the instruction set is highly orthogonal and is grouped into four basic categories: byte-oriented operations bit-oriented operations literal operations control operations the PIC18C601/801 instruction set summary in table 20-2 lists byte-oriented , bit-oriented , literal and control operations. table 20-1 shows the opcode field descriptions. most byte-oriented instructions have three operands: 1. the file register (represented by ? f ? ) 2. the destination of the result (represented by ? d ? ) 3. the accessed memory (represented by ? a ? ) the file register designator ? f ? specifies which file regis- ter is to be used by the instruction. the destination designator ? d ? specifies where the result of the operation is to be placed. if 'd' is zero, the result is placed in the wreg register. if 'd' is one, the result is placed in the file register specified in the instruction. all bit-oriented instructions have three operands: 1. the file register (represented by ? f ? ) 2. the bit in the file register (represented by ? b ? ) 3. the accessed memory (represented by ? a ? ) the bit field designator 'b' selects the number of the bit affected by the operation, while the file register desig- nator 'f' represents the number of the file in which the bit is located. the literal instructions may use some of the following operands: a literal value to be loaded into a file register (represented by ? k ? ) the desired fsr register to load the literal value into (represented by ? f ? ) no operand required (specified by ??? ) the control instructions may use some of the following operands: a program memory address (represented by ? n ? ) the mode of the call or return instructions (represented by ? s ? ) the mode of the table read and table write instructions (represented by ? m ? ) no operand required (specified by ??? ) all instructions are a single word, except for four double word instructions. these four instructions were made double word instructions so that all the required infor- mation is available in these 32 bits. in the second word, the 4 msbs are 1 ? s. if this second word is executed as an instruction (by itself), it will execute as a nop . all single word instructions are executed in a single instruction cycle, unless a conditional test is true, or the program counter is changed as a result of the instruc- tion. in these cases, the execution takes two instruction cycles, with the additional instruction cycle(s) executed as a nop .the double word instructions execute in two instruction cycles. one instruction cycle consists of four oscillator periods. thus, for an oscillator frequency of 4 mhz, the normal instruction execution time is 1 s. if a conditional test is true, or the program counter is changed as a result of an instruction, the instruction execution time is 2 s. two word branch instructions (if true) would take 3 s. figure 20-1 shows the general formats that the instruc- tions can have. all examples use the format ? nnh ? to represent a hexadecimal number, where ? h ? signifies a hexadecimal digit. the instruction set summary, shown in table 20-2, lists the instructions recognized by the microchip assembler (mpasm tm ). section 20.1 provides a description of each instruction.
PIC18C601/801 ds39541a-page 216 advance information ? 2001 microchip technology inc. table 20-1: opcode field descriptions field description a ram access bit a = 0: ram location in access ram (bsr register is ignored) a = 1: ram bank is specified by bsr register access access = 0: ram access bit symbol banked banked = 1: ram access bit symbol bbb bit address within an 8-bit file register (0 to 7) bsr bank select register. used to select the current ram bank. d destination select bit; d = 0: store result in wreg, d = 1: store result in file register f. dest destination either the wreg register or the specified register file location f 8-bit register file address (00h to ffh) f s 12-bit register file address (000h to fffh). this is the source address. f d 12-bit register file address (000h to fffh). this is the destination address. k literal field, constant data or label (may be either an 8-bit, 12-bit or a 20-bit value) label label name mm the mode of the tblptr register for the table read and table write instructions only used with table read and table write instructions: * no change to register (such as tblptr with table reads and writes) *+ post-increment register (such as tblptr with table reads and writes) *- post-decrement register (such as tblptr with table reads and writes) +* pre-increment register (such as tblptr with table reads and writes) n the relative address (2 ? s complement number) for relative branch instructions, or the direct address for call/branch and return instructions prodh product of multiply high byte (register at address ff4h) prodl product of multiply low byte (register at address ff3h) s fast call / return mode select bit. s = 0: do not update into/from shadow registers s = 1: certain registers loaded into/from shadow registers (fast mode) u unused or unchanged (register at address fe8h) w w = 0: destination select bit symbol wreg working register (accumulator) (register at address fe8h) x don't care (0 or 1) the assembler will generate code with x = 0. it is the recommended form of use for compatibility with all microchip software tools. tblptr 21-bit table pointer (points to a program memory location) (register at address ff6h) tablat 8-bit table latch (register at address ff5h) tos to p - o f - st a c k pc program counter pcl program counter low byte (register at address ff9h) pch program counter high byte pclath program counter high byte latch (register at address ffah) pclatu program counter upper byte latch (register at address ffbh) gie global interrupt enable bit wdt watchdog timer to time-out bit pd power-down bit c, dc, z, ov, n alu status bits carry, digit carry, zero, overflow, negative [ ] optional ( ) contents assigned to < > register bit field in the set of italics user defined term (font is courier)
? 2001 microchip technology inc. advance information ds39541a-page 217 PIC18C601/801 figure 20-1: general format for instructions byte-oriented file register operations 15 10 9 8 7 0 d = 0 for result destination to be wreg register opcode d a f (file #) d = 1 for result destination to be file register (f) a = 0 to force access bank bit-oriented file register operations 15 12 11 9 8 7 0 opcode b (bit #) a f (file #) b = 3-bit position of bit in file register (f) literal operations 15 8 7 0 opcode k (literal) k = 8-bit immediate value byte to byte move operations (2-word) 15 12 11 0 opcode f (source file #) call, goto and branch operations 15 8 7 0 opcode n<7:0> (literal) n = 20-bit immediate value a = 1 for bsr to select bank f = 8-bit file register address a = 0 to force access bank a = 1 for bsr to select bank f = 8-bit file register address 15 12 11 0 1111 n<19:8> (literal) 15 12 11 0 1111 f (destination file #) f = 12-bit file register address control operations example instruction addwf myreg, w movff myreg1, myreg2 bsf myreg, bit movlw 7fh goto label 15 8 7 0 opcode n<7:0> (literal) 15 12 11 0 n<19:8> (literal) call myfunc 15 11 10 0 opcode n<10:0> (literal) s = fast bit bra myfunc 15 8 7 0 opcode n<7:0> (literal) bc myfunc s 1111 15 6 4 0 opcode 15 11 7 0 k<7:0> (literal) lfsr fsr0, 100h f k<11:8>(lit.) 1111 0000
PIC18C601/801 ds39541a-page 218 advance information ? 2001 microchip technology inc. table 20-2: PIC18C601/801 instruction set mnemonic, operands description cycles 16-bit instruction word status affected notes msb lsb byte-oriented file register operations addwf addwfc andwf clrf comf cpfseq cpfsgt cpfslt decf decfsz dcfsnz incf incfsz infsnz iorwf movf movff movwf mulwf negf rlcf rlncf rrcf rrncf setf subfwb subwf subwfb swapf tstfsz xorwf f [,d [,a]] f [,d [,a]] f [,d [,a]] f [,a] f [,d [,a]] f [,a] f [,a] f [,a] f [,d [,a]] f [,d [,a]] f [,d [,a]] f [,d [,a]] f [,d [,a]] f [,d [,a]] f [,d [,a]] f [,d [,a]] f s , f d f [,a] f [,a] f [,a] f [,d [,a]] f [,d [,a]] f [,d [,a]] f [,d [,a]] f [,a] f [,d [,a]] f [,d [,a]] f [,d [,a]] f [,d [,a]] f [,a] f [,d [,a]] add wreg and f add wreg and carry bit to f and wreg with f clear f complement f compare f with wreg, skip = compare f with wreg, skip > compare f with wreg, skip < decrement f decrement f, skip if 0 decrement f, skip if not 0 increment f increment f, skip if 0 increment f, skip if not 0 inclusive or wreg with f move f move f s (source) to 1st word f d (destination)2nd word move wreg to f multiply wreg with f negate f rotate left f through carry rotate left f (no carry) rotate right f through carry rotate right f (no carry) set f subtract f from wreg with borrow subtract wreg from f subtract wreg from f with borrow swap nibbles in f test f, skip if 0 exclusive or wreg with f 1 1 1 1 1 1 (2 or 3) 1 (2 or 3) 1 (2 or 3) 1 1 (2 or 3) 1 (2 or 3) 1 1 (2 or 3) 1 (2 or 3) 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 (2 or 3) 1 0010 0010 0001 0110 0001 0110 0110 0110 0000 0010 0100 0010 0011 0100 0001 0101 1100 1111 0110 0000 0110 0011 0100 0011 0100 0110 0101 0101 0101 0011 0110 0001 01da 01da 01da 101a 11da 001a 010a 000a 01da 11da 11da 10da 11da 10da 00da 00da ffff ffff 111a 001a 110a 01da 01da 00da 00da 100a 01da 11da 10da 10da 011a 10da ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff c, dc, z, ov, n c, dc, z, ov, n z, n z z, n none none none c, dc, z, ov, n none none c, dc, z, ov, n none none z, n z, n none none none c, dc, z, ov, n c, z, n z, n c, z, n z, n none c, dc, z, ov, n c, dc, z, ov, n c, dc, z, ov, n none none z, n 1, 2, 6 1, 2, 6 1,2, 6 2, 6 1, 2, 6 4, 6 4, 6 1, 2, 6 1, 2, 3, 4, 6 1, 2, 3, 4, 6 1, 2, 6 1, 2, 3, 4, 6 4, 6 1, 2, 6 1, 2, 6 1, 6 6 6 1, 2, 6 6 1, 2, 6 6 6 6 1, 2, 6 6 1, 2, 6 4, 6 1, 2, 6 6 bit-oriented file register operations bcf bsf btfsc btfss btg f, b [,a] f, b [,a] f, b [,a] f, b [,a] f [,d [,a]] bit clear f bit set f bit test f, skip if clear bit test f, skip if set bit toggle f 1 1 1 (2 or 3) 1 (2 or 3) 1 1001 1000 1011 1010 0111 bbba bbba bbba bbba bbba ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff none none none none none 1, 2, 6 1, 2, 6 3, 4, 6 3, 4, 6 1, 2, 6 note 1: when a port register is modified as a function of itself (e.g., movf portb, 1, 0 ), the value used will be that value present on the pins themselves. for example, if the data latch is ? 1 ? for a pin configured as input and is driven low by an external device, the data will be written back with a ? 0 ? . 2: if this instruction is executed on the tmr0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned. 3: if program counter (pc) is modified, or a conditional test is true, the instruction requires two cycles. the second cycle is executed as a nop . 4: some instructions are 2-word instructions. the second word of these instructions will be executed as a nop , unless the first word of the instruction retrieves the information embedded in these 16-bits. this ensures that all program memory locations have a valid instruction. 5: if the table write starts the write cycle to internal memory, the write will continue until terminated. 6: microchip ? s mpasm tm assembler automatically defaults destination bit ? d ? to ? 1 ? , while access bit ? a ? defaults to ? 1 ? or ? 0 ? , according to address of register being used.
? 2001 microchip technology inc. advance information ds39541a-page 219 PIC18C601/801 control operations bc bn bnc bnn bnov bnz bov bra bz call clrwdt daw goto nop nop pop push rcall reset retfie retlw return sleep n n n n n n n n n n, s ? ? n ? ? ? ? n s k s ? branch if carry branch if negative branch if not carry branch if not negative branch if not overflow branch if not zero branch if overflow branch unconditionally branch if zero call subroutine1st word 2nd word clear watchdog timer decimal adjust wreg go to address1st word 2nd word no operation no operation (note 4) pop top of return stack (tos) push top of return stack (tos) relative call software device reset return from interrupt enable return with literal in wreg return from subroutine go into standby mode 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 2 1 (2) 1 (2) 1 (2) 2 1 1 2 1 1 1 1 2 1 2 2 2 1 1110 1110 1110 1110 1110 1110 1110 1101 1110 1110 1111 0000 0000 1110 1111 0000 1111 0000 0000 1101 0000 0000 0000 0000 0000 0010 0110 0011 0111 0101 0001 0100 0nnn 0000 110s kkkk 0000 0000 1111 kkkk 0000 xxxx 0000 0000 1nnn 0000 0000 1100 0000 0000 nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn kkkk kkkk 0000 0000 kkkk kkkk 0000 xxxx 0000 0000 nnnn 1111 0001 kkkk 0001 0000 nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn kkkk kkkk 0100 0111 kkkk kkkk 0000 xxxx 0110 0101 nnnn 1111 000s kkkk 001s 0011 none none none none none none none none none none to , pd c none none none none none none all gie/gieh, peie/giel none none to , pd table 20-2: PIC18C601/801 instruction set (continued) mnemonic, operands description cycles 16-bit instruction word status affected notes msb lsb note 1: when a port register is modified as a function of itself (e.g., movf portb, 1, 0 ), the value used will be that value present on the pins themselves. for example, if the data latch is '1' for a pin configured as input and is driven low by an external device, the data will be written back with a '0'. 2: if this instruction is executed on the tmr0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned. 3: if program counter (pc) is modified, or a conditional test is true, the instruction requires two cycles. the second cycle is executed as a nop . 4: some instructions are 2-word instructions. the second word of these instructions will be executed as a nop , unless the first word of the instruction retrieves the information embedded in these 16-bits. this ensures that all program memory locations have a valid instruction. 5: if the table write starts the write cycle to internal memory, the write will continue until terminated. 6: microchip ? s mpasm tm assembler automatically defaults destination bit ? d ? to ? 1 ? , while access bit ? a ? defaults to ? 1 ? or ? 0 ? , according to address of register being used.
PIC18C601/801 ds39541a-page 220 advance information ? 2001 microchip technology inc. literal operations addlw andlw iorlw lfsr movlb movlw mullw retlw sublw xorlw k k k f, k k k k k k k add literal and wreg and literal with wreg inclusive or literal with wreg load fsr (f) with a 12-bit literal (k) move literal to bsr<3:0> move literal to wreg multiply literal with wreg return with literal in wreg subtract wreg from literal exclusive or literal with wreg 1 1 1 2 1 1 1 2 1 1 0000 0000 0000 1110 1111 0000 0000 0000 0000 0000 0000 1111 1011 1001 1110 0000 0001 1110 1101 1100 1000 1010 kkkk kkkk kkkk 00ff kkkk 0000 kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk c, dc, z, ov, n z, n z, n none none none none none c, dc, z, ov, n z, n data memory ? program memory operations tblrd* tblrd*+ tblrd*- tblrd+* tblwt* tblwt*+ tblwt*- tblwt+* table read table read with post-increment table read with post-decrement table read with pre-increment table write table write with post-increment table write with post-decrement table write with pre-increment 2 2 (5) 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 1000 1001 1010 1011 1100 1101 1110 1111 none none none none none none none none table 20-2: PIC18C601/801 instruction set (continued) mnemonic, operands description cycles 16-bit instruction word status affected notes msb lsb note 1: when a port register is modified as a function of itself (e.g., movf portb, 1, 0 ), the value used will be that value present on the pins themselves. for example, if the data latch is ? 1 ? for a pin configured as input and is driven low by an external device, the data will be written back with a ? 0 ? . 2: if this instruction is executed on the tmr0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned. 3: if program counter (pc) is modified, or a conditional test is true, the instruction requires two cycles. the second cycle is executed as a nop . 4: some instructions are 2-word instructions. the second word of these instructions will be executed as a nop , unless the first word of the instruction retrieves the information embedded in these 16-bits. this ensures that all program memory locations have a valid instruction. 5: if the table write starts the write cycle to internal memory, the write will continue until terminated. 6: microchip ? s mpasm tm assembler automatically defaults destination bit ? d ? to ? 1 ? , while access bit ? a ? defaults to ? 1 ? or ? 0 ? , according to address of register being used.
? 2001 microchip technology inc. advance information ds39541a-page 221 PIC18C601/801 20.1 instruction set addlw add literal to wreg syntax: [ label ] addlw k operands: 0 k 255 operation: (wreg) + k wreg status affected: n,ov, c, dc, z encoding: 0000 1111 kkkk kkkk description: the contents of wreg are added to the 8-bit literal ? k ? and the result is placed in wreg. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal ? k ? process data write to wreg example : addlw 15h before instruction wreg = 10h n=? ov = ? c=? dc = ? z=? after instruction wreg = 25h n=0 ov = 0 c=0 dc = 0 z=0 addwf add wreg to f syntax: [ label ] addwf f [,d [,a]] operands: 0 f 255 d [0,1] a [0,1] operation: (wreg) + (f) dest status affected: n,ov, c, dc, z encoding: 0010 01da ffff ffff description: add wreg to register ? f ? . if ? d ? is 0, the result is stored in wreg. if ? d ? is 1, the result is stored back in register 'f' (default). if ? a ? is 0, the access bank will be selected. if ? a ? is 1, the bank will be selected as per the bsr value. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ? f ? process data write to destination example : addwf reg, w before instruction wreg = 17h reg = 0c2h n=? ov = ? c=? dc = ? z=? after instruction wreg = 0d9h reg = 0c2h n=1 ov = 0 c=0 dc = 0 z=0
PIC18C601/801 ds39541a-page 222 advance information ? 2001 microchip technology inc. addwfc add wreg and carry bit to f syntax: [ label ] addwfc f [,d [,a]] operands: 0 f 255 d [0,1] a [0,1] operation: (wreg) + (f) + (c) dest status affected: n,ov, c, dc, z encoding: 0010 00da ffff ffff description: add wreg, the carry flag and data memory location ? f ? . if ? d ? is 0, the result is placed in wreg. if ? d ? is 1, the result is placed in data memory location 'f'. if ? a ? is 0, the access bank will be selected. if ? a ? is 1, the bank will be selected as per the bsr value. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ? f ? process data write to destination example : addwfc reg, w before instruction c=1 reg = 02h wreg = 4dh n= ? ov = ? dc = ? z=? after instruction c=0 reg = 02h wreg = 50h n= 0 ov = 0 dc = 0 z=0 andlw and literal with wreg syntax: [ label ] andlw k operands: 0 k 255 operation: (wreg) .and. k wreg status affected: n,z encoding: 0000 1011 kkkk kkkk description: the contents of wreg are and ? ed with the 8-bit literal 'k'. the result is placed in wreg. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal ? k ? process data write to wreg example : andlw 5fh before instruction wreg = 0a3h n= ? z=? after instruction wreg = 03h n= 0 z=0
? 2001 microchip technology inc. advance information ds39541a-page 223 PIC18C601/801 andwf and wreg with f syntax: [ label ] andwf f [,d [,a]] operands: 0 f 255 d [0,1] a [0,1] operation: (wreg) .and. (f) dest status affected: n,z encoding: 0001 01da ffff ffff description: the contents of wreg are and ? ed with register 'f'. if 'd' is 0, the result is stored in wreg. if 'd' is 1, the result is stored back in register 'f' (default). if ? a ? is 0, the access bank will be selected. if ? a ? is 1, the bank will be selected as per the bsr value. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ? f ? process data write to destination example : andwf reg, w before instruction wreg = 17h reg = 0c2h n= ? z=? after instruction wreg = 02h reg = 0c2h n= 0 z=0 bc branch if carry syntax: [ label ] bc n operands: -128 n 127 operation: if carry bit is ? 1 ? (pc) + 2 + 2n pc status affected: none encoding: 1110 0010 nnnn nnnn description: if the carry bit is ? 1 ? , then the pro- gram will branch. the 2 ? s complement number ? 2n ? is added to the pc. since the pc will have incremented to fetch the next instruction, the new address will be pc+2+2n. this instruction is then a two-cycle instruction. words: 1 cycles: 1(2) q cycle activity: if jump: q1 q2 q3 q4 decode read literal ? n ? process data write to pc no operation no operation no operation no operation if no jump: q1 q2 q3 q4 decode read literal ? n ? process data no operation example : here bc 5 before instruction pc = address (here) after instruction if carry = 1; pc = address (here+12) if carry = 0; pc = address (here+2)
PIC18C601/801 ds39541a-page 224 advance information ? 2001 microchip technology inc. bcf bit clear f syntax: [ label ] bcf f, b [,a] operands: 0 f 255 0 b 7 a [0,1] operation: 0 f status affected: none encoding: 1001 bbba ffff ffff description: bit 'b' in register 'f' is cleared. if ? a ? is 0, the access bank will be selected, overriding the bsr value. if ? a ? = 1, the bank will be selected as per the bsr value. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ? f ? process data write register ? f ? example : bcf flag_reg, 7 before instruction flag_reg = 0c7h after instruction flag_reg = 47h bn branch if negative syntax: [ label ] bn n operands: -128 n 127 operation: if negative bit is ? 1 ? (pc) + 2 + 2n pc status affected: none encoding: 1110 0110 nnnn nnnn description: if the negative bit is ? 1 ? , then the pro- gram will branch. the 2 ? s complement number ? 2n ? is added to the pc. since the pc will have incremented to fetch the next instruction, the new address will be pc+2+2n. this instruction is then a two-cycle instruction. words: 1 cycles: 1(2) q cycle activity: if jump: q1 q2 q3 q4 decode read literal ? n ? process data write to pc no operation no operation no operation no operation if no jump: q1 q2 q3 q4 decode read literal ? n ? process data no operation example : here bn jump before instruction pc = address (here) after instruction if negative = 1; pc = address (jump) if negative = 0; pc = address (here+2)
? 2001 microchip technology inc. advance information ds39541a-page 225 PIC18C601/801 bnc branch if not carry syntax: [ label ] bnc n operands: -128 n 127 operation: if carry bit is ? 0 ? (pc) + 2 + 2n pc status affected: none encoding: 1110 0011 nnnn nnnn description: if the carry bit is ? 0 ? , then the program will branch. the 2 ? s complement number ? 2n ? is added to the pc. since the pc will have incremented to fetch the next instruction, the new address will be pc+2+2n. this instruction is then a two-cycle instruction. words: 1 cycles: 1(2) q cycle activity: if jump: q1 q2 q3 q4 decode read literal ? n ? process data write to pc no operation no operation no operation no operation if no jump: q1 q2 q3 q4 decode read literal ? n ? process data no operation example : here bnc jump before instruction pc = address (here) after instruction if carry = 0; pc = address (jump) if carry = 1; pc = address (here+2) bnn branch if not negative syntax: [ label ] bnn n operands: -128 n 127 operation: if negative bit is ? 0 ? (pc) + 2 + 2n pc status affected: none encoding: 1110 0111 nnnn nnnn description: if the negative bit is ? 0 ? , then the program will branch. the 2 ? s complement number ? 2n ? is added to the pc. since the pc will have incremented to fetch the next instruction, the new address will be pc+2+2n. this instruction is then a two-cycle instruction. words: 1 cycles: 1(2) q cycle activity: if jump: q1 q2 q3 q4 decode read literal ? n ? process data write to pc no operation no operation no operation no operation if no jump: q1 q2 q3 q4 decode read literal ? n ? process data no operation example : here bnn jump before instruction pc = address (here) after instruction if negative = 0; pc = address (jump) if negative = 1; pc = address (here+2)
PIC18C601/801 ds39541a-page 226 advance information ? 2001 microchip technology inc. bnov branch if not overflow syntax: [ label ] bnov n operands: -128 n 127 operation: if overflow bit is ? 0 ? (pc) + 2 + 2n pc status affected: none encoding: 1110 0101 nnnn nnnn description: if the overflow bit is ? 0 ? , then the program will branch. the 2 ? s complement number ? 2n ? is added to the pc. since the pc will have incremented to fetch the next instruction, the new address will be pc+2+2n. this instruction is then a two-cycle instruction. words: 1 cycles: 1(2) q cycle activity: if jump: q1 q2 q3 q4 decode read literal ? n ? process data write to pc no operation no operation no operation no operation if no jump: q1 q2 q3 q4 decode read literal ? n ? process data no operation example : here bnov jump before instruction pc = address (here) after instruction if overflow = 0; pc = address (jump) if overflow = 1; pc = address (here+2) bnz branch if not zero syntax: [ label ] bnz n operands: -128 n 127 operation: if zero bit is ? 0 ? (pc) + 2 + 2n pc status affected: none encoding: 1110 0001 nnnn nnnn description: if the zero bit is ? 0 ? , then the program will branch. the 2 ? s complement number ? 2n ? is added to the pc. since the pc will have incremented to fetch the next instruction, the new address will be pc+2+2n. this instruction is then a two-cycle instruction. words: 1 cycles: 1(2) q cycle activity: if jump: q1 q2 q3 q4 decode read literal ? n ? process data write to pc no operation no operation no operation no operation if no jump: q1 q2 q3 q4 decode read literal ? n ? process data no operation example : here bnz jump before instruction pc = address (here) after instruction if zero = 0; pc = address (jump) if zero = 1; pc = address (here+2)
? 2001 microchip technology inc. advance information ds39541a-page 227 PIC18C601/801 bra unconditional branch syntax: [ label ] bra n operands: -1024 n 1023 operation: (pc) + 2 + 2n pc status affected: none encoding: 1101 0nnn nnnn nnnn description: add the 2 ? s complement number ? 2n ? to the pc. since the pc will have incremented to fetch the next instruction, the new address will be pc+2+2n. this instruction is a two- cycle instruction. words: 1 cycles: 2 q cycle activity: q1 q2 q3 q4 decode read literal ? n ? process data write to pc no operation no operation no operation no operation example : here bra jump before instruction pc = address (here) after instruction pc = address (jump) bsf bit set f syntax: [ label ] bsf f, b [,a] operands: 0 f 255 0 b 7 a [0,1] operation: 1 f status affected: none encoding: 1000 bbba ffff ffff description: bit 'b' in register 'f' is set. if ? a ? is 0 access bank will be selected, over- riding the bsr value. if ? a ? is 1, the bank will be selected as per the bsr value (default). words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ? f ? process data write register ? f ? example : bsf flag_reg, 7 before instruction flag_reg = 0ah after instruction flag_reg = 8ah
PIC18C601/801 ds39541a-page 228 advance information ? 2001 microchip technology inc. btfsc bit test file, skip if clear syntax: [ label ] btfsc f, b [,a] operands: 0 f 255 0 b 7 a [0,1] operation: skip if (f) = 0 status affected: none encoding: 1011 bbba ffff ffff description: if bit 'b' in register ? f' is 0, then the next instruction is skipped. if bit 'b' is 0, then the next instruction fetched during the current instruction execution is discarded, and a nop is executed instead, making this a two- cycle instruction. if ? a ? is 0, the access bank will be selected, overriding the bsr value. if ? a ? is 1, the bank will be selected as per the bsr value. words: 1 cycles: 1(2) note: 3 cycles if skip and followed by a 2-word instruction. q cycle activity: q1 q2 q3 q4 decode read register ? f ? process data no operation if skip: q1 q2 q3 q4 no operation no operation no operation no operation if skip and followed by 2-word instruction: q1 q2 q3 q4 no operation no operation no operation no operation no operation no operation no operation no operation example : here false true btfsc : : flag, 1 before instruction pc = address (here) after instruction if flag<1> = 0; pc = address (true) if flag<1> = 1; pc = address (false) btfss bit test file, skip if set syntax: [ label ] btfss f, b [,a] operands: 0 f 255 0 b < 7 a [0,1] operation: skip if (f) = 1 status affected: none encoding: 1010 bbba ffff ffff description: if bit 'b' in register 'f' is 1 then the next instruction is skipped. if bit 'b' is 1, then the next instruction fetched during the current instruction execution, is discarded and a nop is executed instead, making this a two- cycle instruction. if ? a ? is 0, the access bank will be selected, over- riding the bsr value. if ? a ? is 1, the bank will be selected as per the bsr value. words: 1 cycles: 1(2) note: 3 cycles if skip and followed by a 2-word instruction. q cycle activity: q1 q2 q3 q4 decode read register ? f ? process data no operation if skip: q1 q2 q3 q4 no operation no operation no operation no operation if skip and followed by 2-word instruction: q1 q2 q3 q4 no operation no operation no operation no operation no operation no operation no operation no operation example : here false true btfss : : flag, 1 before instruction pc = address (here) after instruction if flag<1> = 0; pc = address (false) if flag<1> = 1; pc = address (true)
? 2001 microchip technology inc. advance information ds39541a-page 229 PIC18C601/801 btg bit toggle f syntax: [ label ] btg f, b [,a] operands: 0 f 255 0 b < 7 a [0,1] operation: (f ) f status affected: none encoding: 0111 bbba ffff ffff description: bit ? b ? in data memory location ? f ? is inverted. if ? a ? is 0, the access bank will be selected, overriding the bsr value. if ? a ? is 1, the bank will be selected as per the bsr value. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ? f ? process data write register ? f ? example : btg portc, 4 before instruction: portc = 0111 0101 [75h] after instruction: portc = 0110 0101 [65h] bov branch if overflow syntax: [ label ] bov n operands: -128 n 127 operation: if overflow bit is ? 1 ? (pc) + 2 + 2n pc status affected: none encoding: 1110 0100 nnnn nnnn description: if the overflow bit is ? 1 ? , then the pro- gram will branch. the 2 ? s complement number ? 2n ? is added to the pc. since the pc will have incremented to fetch the next instruction, the new address will be pc+2+2n. this instruction is then a two-cycle instruction. words: 1 cycles: 1(2) q cycle activity: if jump: q1 q2 q3 q4 decode read literal ? n ? process data write to pc no operation no operation no operation no operation if no jump: q1 q2 q3 q4 decode read literal ? n ? process data no operation example : here bov jump before instruction pc = address (here) after instruction if overflow = 1; pc = address (jump) if overflow = 0; pc = address (here+2)
PIC18C601/801 ds39541a-page 230 advance information ? 2001 microchip technology inc. bz branch if zero syntax: [ label ] bz n operands: -128 n 127 operation: if zero bit is ? 1 ? (pc) + 2 + 2n pc status affected: none encoding: 1110 0000 nnnn nnnn description: if the zero bit is ? 1 ? , then the program will branch. the 2 ? s complement number ? 2n ? is added to the pc. since the pc will have incremented to fetch the next instruction, the new address will be pc+2+2n. this instruction is then a two-cycle instruction. words: 1 cycles: 1(2) q cycle activity: if jump: q1 q2 q3 q4 decode read literal ? n ? process data write to pc no operation no operation no operation no operation if no jump: q1 q2 q3 q4 decode read literal ? n ? process data no operation example : here bz jump before instruction pc = address (here) after instruction if zero = 1; pc = address (jump) if zero = 0; pc = address (here+2) call subroutine call syntax: [ label ] call k [,s] operands: 0 k 1048575 s [0,1] operation: (pc) + 4 tos, k pc<20:1>, if s = 1 (wreg) ws, (status) statuss, (bsr) bsrs status affected: none encoding: 1st word (k<7:0>) 2nd word(k<19:8>) 1110 1111 110s k 19 kkk k 7 kkk kkkk kkkk 0 kkkk 8 description: subroutine call of entire 2m byte memory range. first, return address (pc+ 4) is pushed onto the return stack. if ? s ? = 1, the wreg, status and bsr registers are also pushed into their respective shadow regis- ters, ws, statuss and bsrs. if 's' = 0, no update occurs (default). then the 20-bit value ? k ? is loaded into pc<20:1>. call is a two-cycle instruction. words: 2 cycles: 2 q cycle activity: q1 q2 q3 q4 decode read literal ? k ? <7:0>, push pc to stack read literal ? k ? <19:8>, write to pc no operation no operation no operation no operation example : here call there, fast before instruction pc = address (here) after instruction pc = address (there) tos = address (here + 4) ws = wregreg bsrs = bsr statuss = status
? 2001 microchip technology inc. advance information ds39541a-page 231 PIC18C601/801 clrf clear f syntax: [ label ] clrf f [,a] operands: 0 f 255 a [0,1] operation: 000h f 1 z status affected: z encoding: 0110 101a ffff ffff description: clears the contents of the specified register. if ? a ? is 0, the access bank will be selected, overriding the bsr value. if ? a ? is 1, the bank will be selected as per the bsr value. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ? f ? process data write register ? f ? example : clrf flag_reg before instruction flag_reg = 5ah z=? after instruction flag_reg = 00h z=0 clrwdt clear watchdog timer syntax: [ label ] clrwdt operands: none operation: 000h wdt, 000h wdt postscaler, 1 to, 1 pd status affected: to , pd encoding: 0000 0000 0000 0100 description: clrwdt instruction resets the watchdog timer. it also resets the postscaler of the wdt. status bits to and pd are set. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode no operation process data no operation example : clrwdt before instruction wdt counter = ? wdt postscaler = ? to =? pd =? after instruction wdt counter = 00h wdt postscaler = 0 to =1 pd =1
PIC18C601/801 ds39541a-page 232 advance information ? 2001 microchip technology inc. comf complement f syntax: [ label ] comf f [,d [,a]] operands: 0 f 255 d [0,1] a [0,1] operation: dest status affected: n,z encoding: 0001 11da ffff ffff description: the contents of register ? f ? are com- plemented. if ? d ? is 0 the result is stored in wreg. if ? d ? is 1 the result is stored back in register ? f ? (default). if ? a ? is 0, the access bank will be selected, overriding the bsr value. if ? a ? is 1, the bank will be selected as per the bsr value. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ? f ? process data write to destination example : comf reg before instruction reg = 13h n=? z=? after instruction reg = 13h wreg = 0ech n=1 z=0 (f) cpfseq compare f with wreg, skip if f = wreg syntax: [ label ] cpfseq f [,a] operands: 0 f 255 a [0,1] operation: (f) ? (wreg), skip if (f) = (wreg) (unsigned comparison) status affected: none encoding: 0110 001a ffff ffff description: compares the contents of data memory location 'f' to the contents of wreg by performing an unsigned subtraction. if 'f' = wreg , then the fetched instruction is discarded and a nop is executed instead making this a two-cycle instruction. if ? a ? is 0, the access bank will be selected, over- riding the bsr value. if ? a ? is 1, the bank will be selected as per the bsr value. words: 1 cycles: 1(2) note: 3 cycles if skip and followed by a 2-word instruction. q cycle activity: q1 q2 q3 q4 decode read register ? f ? process data no operation if skip: q1 q2 q3 q4 no operation no operation no operation no operation if skip and followed by 2-word instruction: q1 q2 q3 q4 no operation no operation no operation no operation no operation no operation no operation no operation example : here cpfseq reg nequal : equal : before instruction pc address = here wreg = ? reg = ? after instruction if reg = wreg; pc = address (equal) if reg wreg; pc = address (nequal)
? 2001 microchip technology inc. advance information ds39541a-page 233 PIC18C601/801 cpfsgt compare f with wreg, skip if f > wreg syntax: [ label ] cpfsgt f [,a] operands: 0 f 255 a [0,1] operation: (f) ? ( wreg), skip if (f) > (wreg) (unsigned comparison) status affected: none encoding: 0110 010a ffff ffff description: compares the contents of data memory location ? f ? to the contents of the wreg by performing an unsigned subtraction. if the contents of ? f ? are greater than the contents of , then the fetched instruction is discarded and a nop is executed instead, making this a two-cycle instruction. if ? a ? is 0, the access bank will be selected, over- riding the bsr value. if ? a ? is 1, the bank will be selected as per the bsr value. words: 1 cycles: 1(2) note: 3 cycles if skip and followed by a 2-word instruction. q cycle activity: q1 q2 q3 q4 decode read register ? f ? process data no operation if skip: q1 q2 q3 q4 no operation no operation no operation no operation if skip and followed by 2-word instruction: q1 q2 q3 q4 no operation no operation no operation no operation no operation no operation no operation no operation example : here cpfsgt reg ngreater : greater : before instruction pc = address (here) wreg = ? after instruction if reg > wreg; pc = address (greater) if reg wreg; pc = address (ngreater) cpfslt compare f with wreg, skip if f < wreg syntax: [ label ] cpfslt f [,a] operands: 0 f 255 a [0,1] operation: (f) ? ( wreg), skip if (f) < (wreg) (unsigned comparison) status affected: none encoding: 0110 000a ffff ffff description: compares the contents of data memory location 'f' to the contents of wreg by performing an unsigned subtraction. if the contents of 'f' are less than the contents of wreg, then the fetched instruction is discarded and a nop is executed instead, making this a two-cycle instruction. if ? a ? is 0, the access bank will be selected. if ? a ? is 1, the bank will be selected as per the bsr value. words: 1 cycles: 1(2) note: 3 cycles if skip and followed by a 2-word instruction. q cycle activity: q1 q2 q3 q4 decode read register ? f ? process data no operation if skip: q1 q2 q3 q4 no operation no operation no operation no operation if skip and followed by 2-word instruction: q1 q2 q3 q4 no operation no operation no operation no operation no operation no operation no operation no operation example : here cpfslt reg nless : less : before instruction pc = address (here) wreg = ? after instruction if reg < wreg; pc = address (less) if reg wreg; pc = address (nless)
PIC18C601/801 ds39541a-page 234 advance information ? 2001 microchip technology inc. daw decimal adjust wreg register syntax: [ label ] daw operands: none operation: if [wreg<3:0> >9] or [dc = 1] then (wreg<3:0>) + 6 w<3:0>; else ( wreg<3:0>) w<3:0>; if [wreg<7:4> >9] or [c = 1] then ( wreg<7:4>) + 6 wreg<7:4>; else (wreg<7:4>) wreg<7:4>; status affected: c encoding: 0000 0000 0000 0111 description: daw adjusts the eight-bit value in wreg resulting from the earlier addition of two variables (each in packed bcd format) and produces a correct packed bcd result. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register wreg process data write wreg example1 : daw before instruction wreg = 0a5h c=0 dc = 0 after instruction wreg = 05h c=1 dc = 0 example 2 : before instruction wreg = 0ceh c=0 dc = 0 after instruction wreg = 34h c=1 dc = 0 decf decrement f syntax: [ label ] decf f [,d [,a]] operands: 0 f 255 d [0,1] a [0,1] operation: (f) ? 1 dest status affected: c,dc,n,ov,z encoding: 0000 01da ffff ffff description: decrement register 'f'. if 'd' is 0, the result is stored in wreg. if 'd' is 1, the result is stored back in register 'f' (default). if ? a ? is 0, the access bank will be selected, overriding the bsr value. if ? a ? is 1, the bank will be selected as per the bsr value. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ? f ? process data write to destination example : decf cnt before instruction cnt = 01h z=0 after instruction cnt = 00h z=1
? 2001 microchip technology inc. advance information ds39541a-page 235 PIC18C601/801 decfsz decrement f, skip if 0 syntax: [ label ] decfsz f [,d [,a]] operands: 0 f 255 d [0,1] a [0,1] operation: (f) ? 1 dest, skip if result = 0 status affected: none encoding: 0010 11da ffff ffff description: the contents of register 'f' are decre- mented. if 'd' is 0, the result is placed in wreg. if 'd' is 1, the result is placed back in register 'f' (default). if the result is 0, the next instruction, which is already fetched, is dis- carded, and a nop is executed instead, making it a two-cycle instruction. if ? a ? is 0, the access bank will be selected, overriding the bsr value. if ? a ? is 1, the bank will be selected as per the bsr value. words: 1 cycles: 1(2) note: 3 cycles if skip and followed by a 2-word instruction. q cycle activity: q1 q2 q3 q4 decode read register ? f ? process data write to destination if skip: q1 q2 q3 q4 no operation no operation no operation no operation if skip and followed by 2-word instruction: q1 q2 q3 q4 no operation no operation no operation no operation no operation no operation no operation no operation example : here decfsz cnt goto loop continue before instruction pc = address (here) after instruction cnt = cnt - 1 if cnt = 0; pc = address (continue) if cnt 0; pc = address (here+2) dcfsnz decrement f, skip if not 0 syntax: [ label ] dcfsnz f [,d [,a]] operands: 0 f 255 d [0,1] a [0,1] operation: (f) ? 1 dest, skip if result 0 status affected: none encoding: 0100 11da ffff ffff description: the contents of register 'f' are decre- mented. if 'd' is 0, the result is placed in wreg. if 'd' is 1, the result is placed back in register 'f' (default). if the result is not 0, the next instruc- tion, which is already fetched, is discarded, and a nop is executed instead, making it a two-cycle instruction. if ? a ? is 0, the access bank will be selected, overriding the bsr value. if ? a ? is 1, the bank will be selected as per the bsr value. words: 1 cycles: 1(2) note: 3 cycles if skip and followed by a 2-word instruction. q cycle activity: q1 q2 q3 q4 decode read register ? f ? process data write to destination if skip: q1 q2 q3 q4 no operation no operation no operation no operation if skip and followed by 2-word instruction: q1 q2 q3 q4 no operation no operation no operation no operation no operation no operation no operation no operation example : here dcfsnz temp zero : nzero : before instruction temp = ? after instruction temp = temp - 1, if temp = 0; pc = address (zero ) if temp 0; pc = address (nzero)
PIC18C601/801 ds39541a-page 236 advance information ? 2001 microchip technology inc. goto unconditional branch syntax: [ label ] goto k operands: 0 k 1048575 operation: k pc<20:1> status affected: none encoding: 1st word (k<7:0>) 2nd word(k<19:8>) 1110 1111 1111 k 19 kkk k 7 kkk kkkk kkkk 0 kkkk 8 description: goto allows an unconditional branch anywhere within entire 2m byte memory range. the 20-bit value ? k ? is loaded into pc<20:1>. goto is always a two-cycle instruction. words: 2 cycles: 2 q cycle activity: q1 q2 q3 q4 decode read literal ? k ? <7:0>, no operation read literal ? k ? <19:8>, write to pc no operation no operation no operation no operation example : goto there after instruction pc = address (there) incf increment f syntax: [ label ] incf f [,d [,a]] operands: 0 f 255 d [0,1] a [0,1] operation: (f) + 1 dest status affected: c,dc,n,ov,z encoding: 0010 10da ffff ffff description: the contents of register ? f ? are incre- mented. if ? d ? is 0, the result is placed in wreg. if ? d ? is 1, the result is placed back in register ? f ? (default). if ? a ? is 0, the access bank will be selected, overriding the bsr value. if ? a ? is 1, the bank will be selected as per the bsr value. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ? f ? process data write to destination example : incf cnt before instruction cnt = 0ffh z=0 c=? dc = ? after instruction cnt = 00h z=1 c=1 dc = 1
? 2001 microchip technology inc. advance information ds39541a-page 237 PIC18C601/801 incfsz increment f, skip if 0 syntax: [ label ] incfsz f [,d [,a]] operands: 0 f 255 d [0,1] a [0,1] operation: (f) + 1 dest, skip if result = 0 status affected: none encoding: 0011 11da ffff ffff description: the contents of register ? f ? are incre- mented. if ? d ? is 0, the result is placed in wreg. if ? d ? is 1, the result is placed back in register ? f ? (default). if the result is 0, the next instruction, which is already fetched, is dis- carded, and a nop is executed instead, making it a two-cycle instruction. if ? a ? is 0, the access bank will be selected, overriding the bsr value. if ? a ? is 1, the bank will be selected as per the bsr value. words: 1 cycles: 1(2) note: 3 cycles if skip and followed by a 2-word instruction. q cycle activity: q1 q2 q3 q4 decode read register ? f ? process data write to destination if skip: q1 q2 q3 q4 no operation no operation no operation no operation if skip and followed by 2-word instruction: q1 q2 q3 q4 no operation no operation no operation no operation no operation no operation no operation no operation example : here incfsz cnt nzero : zero : before instruction pc = address (here) after instruction cnt = cnt + 1 if cnt = 0; pc = address (zero) if cnt 0; pc = address (nzero) infsnz increment f, skip if not 0 syntax: [ label ] infsnz f [,d [,a]] operands: 0 f 255 d [0,1] a [0,1] operation: (f) + 1 dest, skip if result 0 status affected: none encoding: 0100 10da ffff ffff description: the contents of register 'f' are incre- mented. if 'd' is 0, the result is placed in wreg. if 'd' is 1, the result is placed back in register 'f' (default). if the result is not 0, the next instruc- tion, which is already fetched, is discarded, and a nop is executed instead, making it a two-cycle instruction. if ? a ? is 0, the access bank will be selected, overriding the bsr value. if ? a ? is 1, the bank will be selected as per the bsr value. words: 1 cycles: 1(2) note: 3 cycles if skip and followed by a 2-word instruction. q cycle activity: q1 q2 q3 q4 decode read register ? f ? process data write to destination if skip: q1 q2 q3 q4 no operation no operation no operation no operation if skip and followed by 2-word instruction: q1 q2 q3 q4 no operation no operation no operation no operation no operation no operation no operation no operation example : here infsnz reg zero nzero before instruction pc = address (here) after instruction reg = reg + 1 if reg 0; pc = address (nzero) if reg = 0; pc = address (zero)
PIC18C601/801 ds39541a-page 238 advance information ? 2001 microchip technology inc. iorlw inclusive or literal with wreg syntax: [ label ] iorlw k operands: 0 k 255 operation: (wreg) .or. k wreg status affected: n,z encoding: 0000 1001 kkkk kkkk description: the contents of wreg are or ? ed with the eight bit literal 'k'. the result is placed in wreg. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal ? k ? process data write to wreg example : iorlw 35h before instruction wreg = 9ah n=? z=? after instruction wreg = 0bfh n=1 z=0 iorwf inclusive or wreg with f syntax: [ label ] iorwf f [,d [,a]] operands: 0 f 255 d [0,1] a [0,1] operation: (wreg) .or. (f) dest status affected: n,z encoding: 0001 00da ffff ffff description: inclusive or wreg with register 'f'. if 'd' is 0, the result is placed in wreg. if 'd' is 1, the result is placed back in register 'f' (default). if ? a ? is 0, the access bank will be selected, overriding the bsr value. if ? a ? is 1, the bank will be selected as per the bsr value. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ? f ? process data write to destination example : iorwf result, w before instruction result = 13h wreg = 91h n=? z=? after instruction result = 13h wreg = 93h n=1 z=0
? 2001 microchip technology inc. advance information ds39541a-page 239 PIC18C601/801 lfsr load fsr syntax: [ label ] lfsr f,k operands: 0 f 2 0 k 4095 operation: k fsrf status affected: none encoding: 1110 1111 1110 0000 00ff k 7 kkk k 11 kkk kkkk description: the 12-bit literal ? k ? is loaded into the file select register pointed to by ? f ? . words: 2 cycles: 2 q cycle activity: q1 q2 q3 q4 decode read literal ? k ? msb process data write literal ? k ? msb to fsrfh decode read literal ? k ? lsb process data write literal ? k ? to fsrfl example : lfsr fsr2, 3abh after instruction fsr2h = 03h fsr2l = 0abh movf move f syntax: [ label ] movf f [,d [,a]] operands: 0 f 255 d [0,1] a [0,1] operation: f dest status affected: n,z encoding: 0101 00da ffff ffff description: the contents of register ? f ? is moved to a destination dependent upon the status of ? d ? . if 'd' is 0, the result is placed in wreg. if 'd' is 1, the result is placed back in register 'f' (default). location 'f' can be anywhere in the 256 byte bank. if ? a ? is 0, the access bank will be selected, overriding the bsr value. if ? a ? is 1, the bank will be selected as per the bsr value. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ? f ? process data write wreg example : movf reg, w before instruction reg = 22h wreg = 0ffh n=? z=? after instruction reg = 22h wreg = 22h n=0 z=0
PIC18C601/801 ds39541a-page 240 advance information ? 2001 microchip technology inc. movff move f to f syntax: [ label ] movff f s ,f d operands: 0 f s 4095 0 f d 4095 operation: (f s ) f d status affected: none encoding: 1st word (source) 2nd word (destin.) 1100 1111 ffff ffff ffff ffff fff f s fff f d description: the contents of source register ? f s ? are moved to destination register ? f d ? . location of source ? f s ? can be any- where in the 4096 byte data space (000h to fffh), and location of desti- nation ? f d ? can also be anywhere from 000h to fffh. either source or destination can be wreg (a useful special situation). movff is particularly useful for transferring a data memory location to a peripheral register (such as the transmit buffer or an i/o port). the movff instruction cannot use the pcl, tosu, tosh or tosl as the destination register. words: 2 cycles: 2 (3) q cycle activity: q1 q2 q3 q4 decode read register ? f ? (src) process data no operation decode no operation no dummy read no operation write register ? f ? (dest) example : movff reg1, reg2 before instruction reg1 = 33h reg2 = 11h after instruction reg1 = 33h, reg2 = 33h movlb move literal to low nibble in bsr syntax: [ label ] movlb k operands: 0 k 255 operation: k bsr status affected: none encoding: 0000 0001 kkkk kkkk description: the 8-bit literal ? k ? is loaded into the bank select register (bsr). words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal ? k ? process data write literal ? k ? to bsr example : movlb 05h before instruction bsr register = 02h after instruction bsr register = 05h
? 2001 microchip technology inc. advance information ds39541a-page 241 PIC18C601/801 movlw move literal to wreg syntax: [ label ] movlw k operands: 0 k 255 operation: k wreg status affected: none encoding: 0000 1110 kkkk kkkk description: the eight bit literal ? k ? is loaded into wreg. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal ? k ? process data write to wreg example : movlw 5ah after instruction wreg = 0x5a movwf move wreg to f syntax: [ label ] movwf f [,a] operands: 0 f 255 a [0,1] operation: (wreg) f status affected: none encoding: 0110 111a ffff ffff description: move data from wreg to register ? f ? . location ? f ? can be anywhere in the 256 byte bank. if ? a ? is 0, the access bank will be selected, overriding the bsr value. if ? a ? is 1, the bank will be selected as per the bsr value. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ? f ? process data write register ? f ? example : movwf reg before instruction wreg = 4fh reg = 0ffh after instruction wreg = 4fh reg = 4fh
PIC18C601/801 ds39541a-page 242 advance information ? 2001 microchip technology inc. mullw multiply literal with wreg syntax: [ label ] mullw k operands: 0 k 255 operation: (wreg) x k prodh:prodl status affected: none encoding: 0000 1101 kkkk kkkk description: an unsigned multiplication is carried out between the contents of wreg and the 8-bit literal ? k ? . the 16-bit result is placed in prodh:prodl register pair. prodh contains the high byte. wreg is unchanged. none of the status flags are affected. note that neither overflow nor carry is possible in this operation. a zero result is possible but not detected. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal ? k ? process data write registers prodh: prodl example : mullw c4h before instruction wreg = 0e2h prodh = ? prodl = ? after instruction wreg = 0e2h prodh = 0adh prodl = 08h mulwf multiply wreg with f syntax: [ label ] mulwf f [,a] operands: 0 f 255 a [0,1] operation: (wreg) x (f) prodh:prodl status affected: none encoding: 0000 001a ffff ffff description: an unsigned multiplication is carried out between the contents of wreg and the register file location ? f ? . the 16-bit result is stored in the prodh:prodl register pair. prodh contains the high byte. both wreg and ? f ? are unchanged. none of the status flags are affected. note that neither overflow nor carry is possible in this operation. a zero result is possible but not detected. if ? a ? is 0, the access bank will be selected, overriding the bsr value. if ? a ? is 1, the bank will be selected as per the bsr value. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ? f ? process data write registers prodh: prodl example : mulwf reg before instruction wreg = 0c4h reg = 0b5h prodh = ? prodl = ? after instruction wreg = 0c4h reg = 0b5h prodh = 8ah prodl = 94h
? 2001 microchip technology inc. advance information ds39541a-page 243 PIC18C601/801 negf negate f syntax: [ label ] negf f [,a] operands: 0 f 255 a [0,1] operation: ( f ) + 1 f status affected: n,ov, c, dc, z encoding: 0110 110a ffff ffff description: location ? f ? is negated using two ? s complement. the result is placed in the data memory location 'f'. if ? a ? is 0, the access bank will be selected, overriding the bsr value. if ? a ? is 1, the bank will be selected as per the bsr value. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ? f ? process data write register ? f ? example : negf reg before instruction reg = 0011 1010 [3ah] n=? ov = ? c=? dc = ? z=? after instruction reg = 1100 0110 [0c6h] n=1 ov = 0 c=0 dc = 0 z=0 nop no operation syntax: [ label ] nop operands: none operation: no operation status affected: none encoding: 0000 1111 0000 xxxx 0000 xxxx 0000 xxxx description: no operation. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode no operation no operation no operation example : none.
PIC18C601/801 ds39541a-page 244 advance information ? 2001 microchip technology inc. pop pop top of return stack syntax: [ label ] pop operands: none operation: (tos) bit bucket status affected: none encoding: 0000 0000 0000 0110 description: the tos value is pulled off the return stack and is discarded. the tos value then becomes the previ- ous value that was pushed onto the return stack. this instruction is provided to enable the user to properly manage the return stack to incorporate a soft- ware stack. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode no operation pop tos value no operation example : pop goto new before instruction tos = 0031a2h stack (1 level down) = 014332h after instruction tos = 014332h pc = new push push top of return stack syntax: [ label ] push operands: none operation: (pc+2) tos status affected: none encoding: 0000 0000 0000 0101 description: the pc+2 is pushed onto the top of the return stack. the previous tos value is pushed down on the stack. this instruction allows implementing a software stack by modifying tos, and then push it onto the return stack. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode push pc+2 onto return stack no operation no operation example : push before instruction tos = 00345ah pc = 000124h after instruction pc = 000126h tos = 000126h stack (1 level down) = 00345ah
? 2001 microchip technology inc. advance information ds39541a-page 245 PIC18C601/801 rcall relative call syntax: [ label ] rcall n operands: -1024 n 1023 operation: (pc) + 2 tos, (pc) + 2 + 2n pc status affected: none encoding: 1101 1nnn nnnn nnnn description: subroutine call with a jump up to 1k from the current location. first, return address (pc+2) is pushed onto the stack. then, add the 2 ? s complement number ? 2n ? to the pc. since the pc will have incremented to fetch the next instruction, the new address will be pc+2+2n. this instruction is a two-cycle instruction. words: 1 cycles: 2 q cycle activity: q1 q2 q3 q4 decode read literal ? n ? push pc to stack process data write to pc no operation no operation no operation no operation example : here rcall jump before instruction pc = address (here) after instruction pc = address (jump) tos = address (here+2) reset reset syntax: [ label ] reset operands: none operation: reset all registers and flags that are affected by a mclr reset. status affected: all encoding: 0000 0000 1111 1111 description: this instruction provides a way to execute a mclr reset in software. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode start reset no operation no operation example : reset after instruction registers = reset value flags* = reset value
PIC18C601/801 ds39541a-page 246 advance information ? 2001 microchip technology inc. retfie return from interrupt syntax: [ label ] retfie [s] operands: s [0,1] operation: (tos) pc, 1 gie/gieh or peie/giel, if s = 1 (ws) wreg, (statuss) status, (bsrs) bsr, pclatu, pclath are unchanged. status affected: none encoding: 0000 0000 0001 000s description: return from interrupt. stack is popped and top-of-stack (tos) is loaded into the pc. interrupts are enabled by setting the either the high or low priority global interrupt enable bit. if ? s ? = 1, the contents of the shadow registers ws, statuss and bsrs are loaded into their corresponding registers, wreg, status and bsr. if ? s ? = 0, no update of these registers occurs (default). words: 1 cycles: 2 q cycle activity: q1 q2 q3 q4 decode no operation no operation pop pc from stack set gieh or giel no operation no operation no operation no operation example : retfie 1 after interrupt pc = tos wreg = ws bsr = bsrs status = statuss gie/gieh, peie/giel = 1 retlw return literal to wreg syntax: [ label ] retlw k operands: 0 k 255 operation: k w, (tos) pc, pclatu, pclath are unchanged status affected: none encoding: 0000 1100 kkkk kkkk description: w is loaded with the eight-bit literal 'k'. the program counter is loaded from the top of the stack (the return address). the high address latch (pclath) remains unchanged. words: 1 cycles: 2 q cycle activity: q1 q2 q3 q4 decode read literal ? k ? process data pop pc from stack, write to wreg no operation no operation no operation no operation example : call table ; wreg contains table ; offset value ; wreg now has ; table value : table addwf pcl ; wreg = offset retlw k0 ; begin table retlw k1 ; : : retlw kn ; end of table before instruction wreg = 07h after instruction wreg = value of kn
? 2001 microchip technology inc. advance information ds39541a-page 247 PIC18C601/801 return return from subroutine syntax: [ label ] return [s] operands: s [0,1] operation: (tos) pc, if s = 1 (ws) w, (statuss) status, (bsrs) bsr, pclatu, pclath are unchanged status affected: none encoding: 0000 0000 0001 001s description: return from subroutine. the stack is popped and the top of the stack (tos) is loaded into the program counter. if ? s ? = 1, the contents of the shadow registers ws, sta- tuss and bsrs are loaded into their corresponding registers, wreg, status and bsr. if ? s ? = 0, no update of these registers occurs (default). words: 1 cycles: 2 q cycle activity: q1 q2 q3 q4 decode no operation process data pop pc from stack no operation no operation no operation no operation example : return after call pc = tos return fast before instruction wrg = 04h status = 00h bsr = 00h after instruction wreg = 04h status = 00h bsr = 00h pc = tos rlcf rotate left f through carry syntax: [ label ] rlcf f [,d [,a]] operands: 0 f 255 d [0,1] a [0,1] operation: (f) dest, (f<7>) c, (c) dest<0> status affected: c,n,z encoding: 0011 01da ffff ffff description: the contents of register 'f' are rotated one bit to the left through the carry flag. if 'd' is 0 the result is placed in wreg. if 'd' is 1 the result is stored back in register 'f' (default). if ? a ? is 0, the access bank will be selected, overriding the bsr value. if ? a ? is 1, the bank will be selected as per the bsr value. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ? f ? process data write to destination example : rlcf reg, w before instruction reg = 1110 0110 c=0 n=? z=? after instruction reg = 1110 0110 wreg = 1100 1100 c=1 n=1 z=0 c register f
PIC18C601/801 ds39541a-page 248 advance information ? 2001 microchip technology inc. rlncf rotate left f (no carry) syntax: [ label ] rlncf f [,d [,a]] operands: 0 f 255 d [0,1] a [0,1] operation: (f) dest, (f<7>) dest<0> status affected: n,z encoding: 0100 01da ffff ffff description: the contents of register ? f ? are rotated one bit to the left. if ? d ? is 0 the result is placed in wreg. if ? d ? is 1, the result is stored back in register 'f' (default). if ? a ? is 0, the access bank will be selected, overriding the bsr value. if ? a ? is 1, the bank will be selected as per the bsr value. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ? f ? process data write to destination example : rlncf reg before instruction reg = 1010 1011 n=? z=? after instruction reg = 0101 0111 n=0 z=0 register f rrcf rotate right f through carry syntax: [ label ] rrcf f [,d [,a]] operands: 0 f 255 d [0,1] a [0,1] operation: (f) dest, (f<0>) c, (c) dest<7> status affected: c,n,z encoding: 0011 00da ffff ffff description: the contents of register 'f' are rotated one bit to the right through the carry flag. if 'd' is 0, the result is placed in wreg. if 'd' is 1, the result is placed back in register 'f' (default). if ? a ? is 0, the access bank will be selected, overriding the bsr value. if ? a ? is 1, the bank will be selected as per the bsr value. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ? f ? process data write to destination example : rrcf reg, w before instruction reg = 1110 0110 c=0 n=? z=? after instruction reg = 1110 0110 wreg = 0111 0011 c=0 n=0 z=0 c register f
? 2001 microchip technology inc. advance information ds39541a-page 249 PIC18C601/801 rrncf rotate right f (no carry) syntax: [ label ] rrncf f [,d [,a]] operands: 0 f 255 d [0,1] a [0,1] operation: (f) dest, (f<0>) dest<7> status affected: n,z encoding: 0100 00da ffff ffff description: the contents of register ? f ? are rotated one bit to the right. if ? d ? is 0, the result is placed in wreg. if ? d ? is 1, the result is placed back in regis- ter 'f' (default). if ? a ? is 0, the access bank will be selected, overriding the bsr value. if ? a ? is 1, the bank will be selected as per the bsr value. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ? f ? process data write to destination example 1 : rrncf reg before instruction reg = 1101 0111 n=? z=? after instruction reg = 1110 1011 n=1 z=0 example 2 : rrncf reg, 0, 0 before instruction wreg = ? reg = 1101 0111 n=? z=? after instruction wreg = 1110 1011 reg = 1101 0111 n=1 z=0 register f setf set f syntax: [ label ] setf f [,a] operands: 0 f 255 a [0,1] operation: ffh f status affected: none encoding: 0110 100a ffff ffff description: the contents of the specified register are set to ffh. if ? a ? is 0, the access bank will be selected, overriding the bsr value. if ? a ? is 1, the bank will be selected as per the bsr value. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ? f ? process data write register ? f ? example : setf reg before instruction reg = 5ah after instruction reg = 0ffh
PIC18C601/801 ds39541a-page 250 advance information ? 2001 microchip technology inc. sleep enter sleep mode syntax: [ label ] sleep operands: none operation: 00h wdt, 0 wdt postscaler, 1 to , 0 pd status affected: to , pd encoding: 0000 0000 0000 0011 description: the power-down status bit (pd ) is cleared. the time-out status bit (to ) is set. watchdog timer and its postscaler are cleared. the processor is put into sleep mode with the oscillator stopped. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode no operation process data go to sleep example : sleep before instruction to =? pd =? after instruction to =1 ? pd =0 ? if wdt causes wake-up, this bit is cleared. subfwb subtract f from wreg with borrow syntax: [ label ] subfwb f [,d [,a]] operands: 0 f 255 d [0,1] a [0,1] operation: (wreg) ? (f) ? (c ) dest status affected: n,ov, c, dc, z encoding: 0101 01da ffff ffff description: subtract register 'f' and carry flag (borrow) from wreg (2 ? s comple- ment method). if 'd' is 0, the result is stored in wreg. if 'd' is 1, the result is stored in register 'f' (default) . if ? a ? is 0, the access bank will be selected, overriding the bsr value. if ? a ? is 1, the bank will be selected as per the bsr value. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ? f ? process data write to destination
? 2001 microchip technology inc. advance information ds39541a-page 251 PIC18C601/801 subfwb (cont.) example 1 : subfwb reg before instruction reg = 3 wreg = 2 c=1 after instruction reg = 0ffh wreg = 2 c=0 z=0 n = 1 ; result is negative example 2 : subfwb reg before instruction reg = 2 wreg = 5 c=1 after instruction reg = 2 wreg = 3 c=1 z=0 n = 0 ; result is positive example 3 : subfwb reg before instruction reg = 1 wreg = 2 c=0 after instruction reg = 0 wreg = 2 c=1 z = 1 ; result is zero n=0 sublw subtract wreg from literal syntax: [ label ]sublw k operands: 0 k 255 operation: k ? (wreg) wreg status affected: n,ov, c, dc, z encoding: 0000 1000 kkkk kkkk description: wreg is subtracted from the eight bit literal 'k'. the result is placed in wreg. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal ? k ? process data write to wreg example 1: sublw 02h before instruction wreg = 1 c=? after instruction wreg = 1 c = 1 ; result is positive z=0 n=0 example 2 : sublw 02h before instruction wreg = 2 c=? after instruction wreg = 0 c = 1 ; result is zero z=1 n=0 example 3 : sublw 02h before instruction wreg = 3 c=? after instruction wreg = 0ffh ; (2 ? s complement) c = 0 ; result is negative z=0 n=1
PIC18C601/801 ds39541a-page 252 advance information ? 2001 microchip technology inc. subwf subtract wreg from f syntax: [ label ] subwf f [,d [,a]] operands: 0 f 255 d [0,1] a [0,1] operation: (f) ? (wreg) dest status affected: n,ov, c, dc, z encoding: 0101 11da ffff ffff description: subtract wreg from register 'f' (2 ? s complement method). if 'd' is 0, the result is stored in wreg. if 'd' is 1, the result is stored back in reg- ister 'f' (default). if ? a ? is 0, the access bank will be selected, over- riding the bsr value. if ? a ? is 1, the bank will be selected as per the bsr value. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ? f ? process data write to destination subwf (cont.) example 1 : subwf reg before instruction reg = 3 wreg = 2 c=? after instruction reg = 1 wreg = 2 c = 1 ; result is positive z=0 n=0 example 2 : subwf reg, w before instruction reg = 2 wreg = 2 c=? after instruction reg = 2 wreg = 0 c = 1 ; result is zero z=1 n=0 example 3 : subwf reg before instruction reg = 1 wreg = 2 c=? after instruction reg = 0ffh ;(2 ? s complement) wreg = 2 c = 0 ; result is negative z=0 n=1
? 2001 microchip technology inc. advance information ds39541a-page 253 PIC18C601/801 subwfb subtract wreg from f with borrow syntax: [ label ] subwfb f [,d [,a]] operands: 0 f 255 d [0,1] a [0,1] operation: (f) ? (wreg) ? (c ) dest status affected: n,ov, c, dc, z encoding: 0101 10da ffff ffff description: subtract wreg and the carry flag (borrow) from register 'f' (2 ? s com- plement method). if 'd' is 0, the result is stored in wreg. if 'd' is 1, the result is stored back in register 'f' (default). if ? a ? is 0, the access bank will be selected, overriding the bsr value. if ? a ? is 1, the bank will be selected as per the bsr value. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ? f ? process data write to destination subwfb (cont.) example 1 : subwfb reg before instruction reg = 19h ( 0001 1001 ) wreg = 0dh ( 0000 1101 ) c=1 after instruction reg = 0ch ( 0000 1011 ) wreg = 0dh ( 0000 1101 ) c=1 z=0 n = 0 ; result is positive example 2 : subwfb reg, w before instruction reg = 1bh ( 0001 1011 ) wreg = 1ah ( 0001 1010 ) c=0 after instruction reg = 1bh ( 0001 1011 ) wreg = 00h c=1 z = 1 ; result is zero n=0 example 3 : subwfb reg before instruction reg = 03h ( 0000 0011 ) wreg = 0eh ( 0000 1101 ) c=1 after instruction reg = 0f5h ( 1111 0100 ) [2 ? s comp] wreg = 0eh ( 0000 1101 ) c=0 z=0 n = 1 ; result is negative
PIC18C601/801 ds39541a-page 254 advance information ? 2001 microchip technology inc. swapf swap nibbles in f syntax: [ label ] swapf f [,d [,a]] operands: 0 f 255 d [0,1] a [0,1] operation: (f<3:0>) dest<7:4>, (f<7:4>) dest<3:0> status affected: none encoding: 0011 10da ffff ffff description: the upper and lower nibbles of reg- ister ? f ? are exchanged. if ? d ? is 0, the result is placed in wreg. if ? d ? is 1, the result is placed in register ? f ? (default). if ? a ? is 0, the access bank will be selected, overriding the bsr value. if ? a ? is 1, the bank will be selected as per the bsr value. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ? f ? process data write to destination example : swapf reg before instruction reg = 53h after instruction reg = 35h
? 2001 microchip technology inc. advance information ds39541a-page 255 PIC18C601/801 tblrd table read syntax: [ label ] tblrd ( *; *+; *-; +*) operands: none operation: if tblrd *, (prog mem (tblptr)) tablat; tblptr - no change; if tblrd *+, (prog mem (tblptr)) tablat; (tblptr) +1 tblptr; if tblrd *-, (prog mem (tblptr)) tablat; (tblptr) -1 tblptr; if tblrd +*, (tblptr) +1 tblptr; (prog mem (tblptr)) tablat; status affected: none encoding: 0000 0000 0000 10nn nn=0 * =1 *+ =2 *- =3 +* description: this instruction is used to read the con- tents of program memory (p.m.). to address the program memory, a pointer called table pointer (tblptr) is used. the tblptr (a 21-bit pointer) points to each byte in the program memory. tblptr has a 2 mbyte address range. tblptr[0] = 0: least significant byte of program memory word tblptr[0] = 1: most significant byte of program memory word the tblrd instruction can modify the value of tblptr as follows: no change post-increment post-decrement pre-increment words: 1 cycles: 2 q cycle activity: q1 q2 q3 q4 decode no operation no operation no operation no operation no operation (read program memory) no operation no operation (write tablat) tblrd (cont.) example 1 : tblrd *+ ; before instruction tablat = 55h tblptr = 00a356h memory(00a356h) = 34h after instruction tablat = 34h tblptr = 00a357h example 2 : tblrd +* ; before instruction tablat = 0aah tblptr = 01a357h memory(01a357h) = 12h memory(01a358h) = 34h after instruction tablat = 34h tblptr = 01a358h
PIC18C601/801 ds39541a-page 256 advance information ? 2001 microchip technology inc. tblwt table write syntax: [ label ] tblwt ( *; *+; *-; +*) operands: none operation: if tblwt*, (tablat) prog mem (tblptr) or holding register; tblptr - no change; if tblwt*+, (tablat) prog mem (tblptr) or holding register; (tblptr) +1 tblptr; if tblwt*-, (tablat) prog mem (tblptr) or holding register; (tblptr) -1 tblptr; if tblwt+*, (tblptr) +1 tblptr; (tablat) prog mem (tblptr) or holding register; status affected: none encoding: 0000 0000 0000 11nn nn=0 * =1 *+ =2 *- =3 +* description: this instruction is used to program the contents of program memory (p.m.). the tblptr (a 21-bit pointer) points to each byte in the program memory. tblptr has a 2 mbyte address range. the lsb of the tblptr selects which byte of the program memory location to access. tblptr[0] = 0:least significant byte of program memory word tblptr[0] = 1:most significant byte of program memory word the tblwt instruction can modify the value of tblptr as follows: no change post-increment post-decrement pre-increment words: 1 cycles: 2 (many if long write is to on-chip eprom program memory) q cycle activity: q1 q2 q3 q4 decode no operation no operation no operation no operation no operation (read tablat) no operation no operation (write to holding register or memory) tblwt (cont.) example 1 : tblwt *+; before instruction tablat = 55h tblptr = 00a356h memory(00a356h) = 0ffh after instructions (table write completion) tablat = 55h tblptr = 00a357h memory(00a356h) = 55h example 2 : tblwt +*; before instruction tablat = 34h tblptr = 01389ah memory(01389ah) = 0ffh memory(01389bh) = 0ffh after instruction (table write completion) tablat = 34h tblptr = 01389bh memory(01389ah) = 0ffh memory(01389bh) = 34h
? 2001 microchip technology inc. advance information ds39541a-page 257 PIC18C601/801 tstfsz test f, skip if 0 syntax: [ label ] tstfsz f [,a] operands: 0 f 255 a [0,1] operation: skip if f = 0 status affected: none encoding: 0110 011a ffff ffff description: if ? f ? = 0, the next instruction, fetched during the current instruction exe- cution, is discarded and a nop is executed, making this a two-cycle instruction. if ? a ? is 0, the access bank will be selected, overriding the bsr value. if ? a ? is 1, the bank will be selected as per the bsr value. words: 1 cycles: 1(2) note: 3 cycles if skip and followed by a 2-word instruction q cycle activity: q1 q2 q3 q4 decode read register ? f ? process data no operation if skip: q1 q2 q3 q4 no operation no operation no operation no operation if skip and followed by 2-word instruction: q1 q2 q3 q4 no operation no operation no operation no operation no operation no operation no operation no operation example : here tstfsz cnt nzero : zero : before instruction pc = address ( here ) after instruction if cnt = 00h, pc = address (zero) if cnt 00h, pc = address (nzero) xorlw exclusive or literal with wreg syntax: [ label ] xorlw k operands: 0 k 255 operation: (wreg) .xor. k wreg status affected: n,z encoding: 0000 1010 kkkk kkkk description: the contents of wreg are xor ? ed with the 8-bit literal 'k'. the result is placed in wreg. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal ? k ? process data write to wreg example : xorlw 0afh before instruction wreg = 0b5h n=? z=? after instruction wreg = 1ah n=0 z=0
PIC18C601/801 ds39541a-page 258 advance information ? 2001 microchip technology inc. xorwf exclusive or wreg with f syntax: [ label ] xorwf f [,d [,a]] operands: 0 f 255 d [0,1] a [0,1] operation: (wreg) .xor. (f) dest status affected: n,z encoding: 0001 10da ffff ffff description: exclusive or the contents of wreg with register ? f ? . if ? d ? is 0, the result is stored in wreg. if ? d ? is 1, the result is stored back in the register ? f ? (default). if ? a ? is 0, the access bank will be selected, overriding the bsr value. if ? a ? is 1, the bank will be selected as per the bsr value. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ? f ? process data write to destination example : xorwf reg before instruction reg = 0afh wreg = 0b5h n=? z=? after instruction reg = 1ah wreg = 0b5h n=0 z=0
? 2001 microchip technology inc. advance information ds39541a-page 259 PIC18C601/801 21.0 development support the picmicro ? microcontrollers are supported with a full range of hardware and software development tools: integrated development environment - mplab ? ide software assemblers/compilers/linkers - mpasm tm assembler - mplab c17 and mplab c18 c compilers -mplink tm object linker/ mplib tm object librarian simulators - mplab sim software simulator emulators - mplab ice 2000 in-circuit emulator - icepic ? in-circuit emulator in-circuit debugger - mplab icd for pic16f87x device programmers -pro mate ? ii universal device programmer - picstart ? plus entry-level development programmer low cost demonstration boards - picdem tm 1 demonstration board - picdem 2 demonstration board - picdem 3 demonstration board - picdem 17 demonstration board -k ee l oq ? demonstration board 21.1 mplab integrated development environment software the mplab ide software brings an ease of software development previously unseen in the 8-bit microcon- troller market. the mplab ide is a windows ? -based application that contains: an interface to debugging tools - simulator - programmer (sold separately) - emulator (sold separately) - in-circuit debugger (sold separately) a full-featured editor a project manager customizable toolbar and key mapping a status bar on-line help the mplab ide allows you to: edit your source files (either assembly or ? c ? ) one touch assemble (or compile) and download to picmicro emulator and simulator tools (auto- matically updates all project information) debug using: - source files - absolute listing file - machine code the ability to use mplab ide with multiple debugging tools allows users to easily switch from the cost- effective simulator to a full-featured emulator with minimal retraining. 21.2 mpasm assembler the mpasm assembler is a full-featured universal macro assembler for all picmicro mcu ? s. the mpasm assembler has a command line interface and a windows shell. it can be used as a stand-alone application on a windows 3.x or greater system, or it can be used through mplab ide. the mpasm assem- bler generates relocatable object files for the mplink object linker, intel ? standard hex files, map files to detail memory usage and symbol reference, an abso- lute lst file that contains source lines and generated machine code, and a cod file for debugging. the mpasm assembler features include: integration into mplab ide projects. user-defined macros to streamline assembly code. conditional assembly for multi-purpose source files. directives that allow complete control over the assembly process. 21.3 mplab c17 and mplab c18 c compilers the mplab c17 and mplab c18 code development systems are complete ansi ? c ? compilers for microchip ? s pic17cxxx and pic18cxxx family of microcontrollers, respectively. these compilers provide powerful integration capabilities and ease of use not found with other compilers. for easier source level debugging, the compilers pro- vide symbol information that is compatible with the mplab ide memory display.
PIC18C601/801 ds39541a-page 260 advance information ? 2001 microchip technology inc. 21.4 mplink object linker/ mplib object librarian the mplink object linker combines relocatable objects created by the mpasm assembler and the mplab c17 and mplab c18 c compilers. it can also link relocatable objects from pre-compiled libraries, using directives from a linker script. the mplib object librarian is a librarian for pre- compiled code to be used with the mplink object linker. when a routine from a library is called from another source file, only the modules that contain that routine will be linked in with the application. this allows large libraries to be used efficiently in many different applications. the mplib object librarian manages the creation and modification of library files. the mplink object linker features include: integration with mpasm assembler and mplab c17 and mplab c18 c compilers. allows all memory areas to be defined as sections to provide link-time flexibility. the mplib object librarian features include: easier linking because single libraries can be included instead of many smaller files. helps keep code maintainable by grouping related modules together. allows libraries to be created and modules to be added, listed, replaced, deleted or extracted. 21.5 mplab sim software simulator the mplab sim software simulator allows code devel- opment in a pc-hosted environment by simulating the picmicro series microcontrollers on an instruction level. on any given instruction, the data areas can be examined or modified and stimuli can be applied from a file, or user-defined key press, to any of the pins. the execution can be performed in single step, execute until break, or trace mode. the mplab sim simulator fully supports symbolic debug- ging using the mplab c17 and the mplab c18 c com- pilers and the mpasm assembler. the software simulator offers the flexibility to develop and debug code outside of the laboratory environment, making it an excellent multi- project software development tool. 21.6 mplab ice high performance universal in-circuit emulator with mplab ide the mplab ice universal in-circuit emulator is intended to provide the product development engineer with a complete microcontroller design tool set for picmicro microcontrollers (mcus). software control of the mplab ice in-circuit emulator is provided by the mplab integrated development environment (ide), which allows editing, building, downloading and source debugging from a single environment. the mplab ice 2000 is a full-featured emulator sys- tem with enhanced trace, trigger and data monitoring features. interchangeable processor modules allow the system to be easily reconfigured for emulation of differ- ent processors. the universal architecture of the mplab ice in-circuit emulator allows expansion to support new picmicro microcontrollers. the mplab ice in-circuit emulator system has been designed as a real-time emulation system, with advanced features that are generally found on more expensive development tools. the pc platform and microsoft ? windows environment were chosen to best make these features available to you, the end user. 21.7 icepic in-circuit emulator the icepic low cost, in-circuit emulator is a solution for the microchip technology pic16c5x, pic16c6x, pic16c7x and pic16cxxx families of 8-bit one- time-programmable (otp) microcontrollers. the mod- ular system can support different subsets of pic16c5x or pic16cxxx products through the use of inter- changeable personality modules, or daughter boards. the emulator is capable of emulating without target application circuitry being present.
? 2001 microchip technology inc. advance information ds39541a-page 261 PIC18C601/801 21.8 mplab icd in-circuit debugger microchip ? s in-circuit debugger, mplab icd, is a pow- erful, low cost, run-time development tool. this tool is based on the flash pic16f87x and can be used to develop for this and other picmicro microcontrollers from the pic16cxxx family. the mplab icd utilizes the in-circuit debugging capability built into the pic16f87x. this feature, along with microchip ? s in-circuit serial programming tm protocol, offers cost- effective in-circuit flash debugging from the graphical user interface of the mplab integrated development environment. this enables a designer to develop and debug source code by watching variables, single- stepping and setting break points. running at full speed enables testing hardware in real-time. 21.9 pro mate ii universal device programmer the pro mate ii universal device programmer is a full-featured programmer, capable of operating in stand-alone mode, as well as pc-hosted mode. the pro mate ii device programmer is ce compliant. the pro mate ii device programmer has program- mable v dd and v pp supplies, which allow it to verify programmed memory at v dd min and v dd max for max- imum reliability. it has an lcd display for instructions and error messages, keys to enter commands and a modular detachable socket assembly to support various package types. in stand-alone mode, the pro mate ii device programmer can read, verify, or program picmicro devices. it can also set code protection in this mode. 21.10 picstart plus entry level development programmer the picstart plus development programmer is an easy-to-use, low cost, prototype programmer. it con- nects to the pc via a com (rs-232) port. mplab integrated development environment software makes using the programmer simple and efficient. the picstart plus development programmer sup- ports all picmicro devices with up to 40 pins. larger pin count devices, such as the pic16c92x and pic17c76x, may be supported with an adapter socket. the picstart plus development programmer is ce compliant. 21.11 picdem 1 low cost picmicro demonstration board the picdem 1 demonstration board is a simple board which demonstrates the capabilities of several of microchip ? s microcontrollers. the microcontrollers sup- ported are: pic16c5x (pic16c54 to pic16c58a), pic16c61, pic16c62x, pic16c71, pic16c8x, pic17c42, pic17c43 and pic17c44. all necessary hardware and software is included to run basic demo programs. the user can program the sample microcon- trollers provided with the picdem 1 demonstration board on a pro mate ii device programmer, or a picstart plus development programmer, and easily test firmware. the user can also connect the picdem 1 demonstration board to the mplab ice in- circuit emulator and download the firmware to the emu- lator for testing. a prototype area is available for the user to build some additional hardware and connect it to the microcontroller socket(s). some of the features include an rs-232 interface, a potentiometer for simu- lated analog input, push button switches and eight leds connected to portb. 21.12 picdem 2 low cost pic16cxx demonstration board the picdem 2 demonstration board is a simple dem- onstration board that supports the pic16c62, pic16c64, pic16c65, pic16c73 and pic16c74 microcontrollers. all the necessary hardware and soft- ware is included to run the basic demonstration pro- grams. the user can program the sample microcontrollers provided with the picdem 2 demon- stration board on a pro mate ii device programmer, or a picstart plus development programmer, and easily test firmware. the mplab ice in-circuit emula- tor may also be used with the picdem 2 demonstration board to test firmware. a prototype area has been pro- vided to the user for adding additional hardware and connecting it to the microcontroller socket(s). some of the features include a rs-232 interface, push button switches, a potentiometer for simulated analog input, a serial eeprom to demonstrate usage of the i 2 c tm bus and separate headers for connection to an lcd module and a keypad.
PIC18C601/801 ds39541a-page 262 advance information ? 2001 microchip technology inc. 21.13 picdem 3 low cost pic16cxxx demonstration board the picdem 3 demonstration board is a simple dem- onstration board that supports the pic16c923 and pic16c924 in the plcc package. it will also support future 44-pin plcc microcontrollers with an lcd mod- ule. all the necessary hardware and software is included to run the basic demonstration programs. the user can program the sample microcontrollers pro- vided with the picdem 3 demonstration board on a pro mate ii device programmer, or a picstart plus development programmer with an adapter socket, and easily test firmware. the mplab ice in-circuit emula- tor may also be used with the picdem 3 demonstration board to test firmware. a prototype area has been pro- vided to the user for adding hardware and connecting it to the microcontroller socket(s). some of the features include a rs-232 interface, push button switches, a potentiometer for simulated analog input, a thermistor and separate headers for connection to an external lcd module and a keypad. also provided on the picdem 3 demonstration board is a lcd panel, with 4 commons and 12 segments, that is capable of display- ing time, temperature and day of the week. the picdem 3 demonstration board provides an additional rs-232 interface and windows software for showing the demultiplexed lcd signals on a pc. a simple serial interface allows the user to construct a hardware demultiplexer for the lcd signals. 21.14 picdem 17 demonstration board the picdem 17 demonstration board is an evaluation board that demonstrates the capabilities of several microchip microcontrollers, including pic17c752, pic17c756a, pic17c762 and pic17c766. all neces- sary hardware is included to run basic demo programs, which are supplied on a 3.5-inch disk. a programmed sample is included and the user may erase it and program it with the other sample programs using the pro mate ii device programmer, or the picstart plus development programmer, and easily debug and test the sample code. in addition, the picdem 17 dem- onstration board supports downloading of programs to and executing out of external flash memory on board. the picdem 17 demonstration board is also usable with the mplab ice in-circuit emulator, or the picmaster emulator and all of the sample programs can be run and modified using either emulator. addition- ally, a generous prototype area is available for user hardware. 21.15 k ee l oq evaluation and programming tools k ee l oq evaluation and programming tools support microchip ? s hcs secure data products. the hcs eval- uation kit includes a lcd display to show changing codes, a decoder to decode transmissions and a pro- gramming interface to program test transmitters.
? 2001 microchip technology inc. advance information ds39541a-page 263 PIC18C601/801 table 21-1: development tools from microchip pic12cxxx pic14000 pic16c5x pic16c6x pic16cxxx pic16f62x pic16c7x pic16c7xx pic16c8x pic16f8xx pic16c9xx pic17c4x pic17c7xx pic18cxx2 24cxx/ 25cxx/ 93cxx hcsxxx mcrfxxx mcp2510 software tools mplab ? integrated development environment mplab ? c17 c compiler mplab ? c18 c compiler mpasm tm assembler/ mplink tm object linker emulators mplab ? ice in-circuit emulator ** icepic tm in-circuit emulator debugger mplab ? icd in-circuit debugger * * programmers picstart ? plus entry level development programmer ** pro mate ? ii universal device programmer ** demo boards and eval kits picdem tm 1 demonstration board ? picdem tm 2 demonstration board ? ? picdem tm 3 demonstration board picdem tm 14a demonstration board picdem tm 17 demonstration board k ee l oq ? evaluation kit k ee l oq ? transponder kit microid tm programmer ? s kit 125 khz microid tm developer ? s kit 125 khz anticollision microid tm developer ? s kit 13.56 mhz anticollision microid tm developer ? s kit mcp2510 can developer ? s kit * contact the microchip technology inc. web site at www.microchip.com for information on how to use the mplab ? icd in-circuit debugger (dv164001) with pic16c62, 63, 64, 65, 72, 73, 74, 76, 77. ** contact microchip technology inc. for availability date. ? development tool is available on select devices.
PIC18C601/801 ds39541a-page 264 advance information ? 2001 microchip technology inc. notes:
? 2001 microchip technology inc. advance information ds39541a-page 265 PIC18C601/801 22.0 electrical characteristics absolute maximum ratings ( ? ) ambient temperature under bias................................................................................................. ............-55 c to +125 c storage temperature ............................................................................................................ .................. -65 c to +150 c voltage on any pin with respect to v ss (except v dd , mclr , and ra4) ......................................... -0.3v to (v dd + 0.3v) voltage on v dd with respect to v ss ......................................................................................................... -0.3v to +7.5v voltage on mclr with respect to v ss (note 2) ......................................................................................... 0v to +13.25v voltage on ra4 with respect to v ss ............................................................................................................... 0v to +8.5v total power dissipation (note 1) ............................................................................................................................... 1.0w maximum current out of v ss pin ........................................................................................................................... 300 ma maximum current into v dd pin ........................................................................................................................... ...250 ma input clamp current, i ik (v i < 0 or v i > v dd ) ...................................................................................................................... 20 ma output clamp current, i ok (v o < 0 or v o > v dd ) .............................................................................................................. 20 ma maximum output current sunk by any i/o pin..................................................................................... .....................25 ma maximum output current sourced by any i/o pin .................................................................................. ..................25 ma maximum current sunk by all ports (combined) ....................................................................................................200 ma maximum current sourced by all ports (combined) ................................................................................ ...............200 ma note 1: power dissipation is calculated as follows: pdis = v dd x {i dd - i oh } + {(v dd -v oh ) x i oh } + (v o l x i ol ) 2: voltage spikes below v ss at the mclr /v pp pin, inducing currents greater than 80 ma, may cause latch-up. thus, a series resistor of 50-100 ? should be used when applying a ? low ? level to the mclr /v pp pin, rather than pulling this pin directly to v ss . ? notice: stresses above those listed under ? absolute maximum ratings ? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability.
PIC18C601/801 ds39541a-page 266 advance information ? 2001 microchip technology inc. figure 22-1: PIC18C601/801 voltage-frequency graph (industrial) figure 22-2: PIC18C601/801 voltage-frequency graph (extended) frequency voltage 6.0 v 5.5 v 4.5 v 4.0 v 2.0 v 25 mhz 5.0 v 3.5 v 3.0 v 2.5 v PIC18C601/801 4.2v frequency voltage 6.0 v 5.5 v 4.5 v 4.0 v 2.0 v 25 mhz 5.0 v 3.5 v 3.0 v 2.5 v PIC18C601/801 f max = (12.0 mhz/v) (v ddappmin - 2.0 v) + 4 mhz where v ddappmin < 3 note: v ddapp is the minimum voltage of the picmicro ? device in the application. 4 mhz 4.2v 16 mhz f max = (7.5 mhz/v) (v ddappmin - 3.0 v) + 16 mhz where v ddappmin > 3
? 2001 microchip technology inc. advance information ds39541a-page 267 PIC18C601/801 22.1 dc characteristics pic18lc601/801 (industrial) standard operating conditions (unless otherwise stated) operating temperature -40 c t a +85 c for industrial PIC18C601/801 (industrial, extended) standard operating conditions (unless otherwise stated) operating temperature -40 c t a +85 c for industrial -40 c t a +125 c for extended param no. symbol characteristic/ device min typ max units conditions d001 v dd supply voltage pic18lc601/801 2.0 ? 5.5 v d001 PIC18C601/801 4.2 ? 5.5 v d002 v dr ram data retention voltage (1) 1.5 ?? v d003 v por v dd start voltage to ensure internal power-on reset signal ?? 0.7 v see section on power-on reset for details d004 s vdd v dd rise rate to ensure internal power- on reset signal 0.05 ?? v/ms see section on power-on reset for details legend: rows with industrial-extended data are shaded for improved readability. note 1: this is the limit to which v dd can be lowered in sleep mode, or during a device reset, without losing ram data. 2: the supply current is mainly a function of the operating voltage and frequency. other factors, such as i/o pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail to rail; all i/o pins tri-stated, pulled to v dd mclr = v dd ; wdt enabled/disabled as specified. 3: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in hi-impedance state and tied to v dd or v ss , and all features that add delta current disabled (such as wdt, timer1 oscillator, bor, ...). 4: for rc osc option, current through r ext is not included. the current through the resistor can be estimated by the formula ir = v dd /2r ext (ma) with r ext in kohm.
PIC18C601/801 ds39541a-page 268 advance information ? 2001 microchip technology inc. d010 i dd supply current (2,4) pic18lc601/801 ? tbd tbd ma rc osc option f osc = 4 mhz, v dd = 2.5v d010 PIC18C601/801 ? tbd tbd ma rc osc options f osc = 4 mhz, v dd = 4.2v d010a pic18lc601/801 ? tbd tbd a lp osc option f osc = 32 khz, v dd = 2.5v d010a PIC18C601/801 ? tbd tbd a lp osc option f osc = 32 khz, v dd = 4.2v d010c pic18lc601/801 ? tbd 45 ma ec osc option, f osc = 25 mhz, v dd = 5.5v d010c PIC18C601/801 ? ? 45 ma ec osc option, f osc = 25 mhz, v dd = 5.5v d013 pic18lc601/801 ? ? ? ? ? ? tbd 50 50 ma ma ma hs osc options f osc = 6 mhz, v dd = 2.5v f osc = 25 mhz, v dd = 5.5v hs + pll osc option f osc = 10 mhz, v dd = 5.5v d013 PIC18C601/801 ? ? ? ? 50 50 ma ma hs osc option f osc = 25 mhz, v dd = 5.5v hs + pll osc option f osc = 10 mhz, v dd = 5.5v d014 pic18lc601/801 ? ? ? ? 48 tbd a a timer1 osc option f osc = 32 khz, v dd = 2.5v f osc = 32 khz, v dd = 2.5v, 25 c d014 PIC18C601/801 ? ? ? ? tbd tbd a a oscb osc option f osc = 32 khz, v dd = 4.2v f osc = 32 khz, v dd = 4.2v, 25 c 22.1 dc characteristics (continued) pic18lc601/801 (industrial) standard operating conditions (unless otherwise stated) operating temperature -40 c t a +85 c for industrial PIC18C601/801 (industrial, extended) standard operating conditions (unless otherwise stated) operating temperature -40 c t a +85 c for industrial -40 c t a +125 c for extended param no. symbol characteristic/ device min typ max units conditions legend: rows with industrial-extended data are shaded for improved readability. note 1: this is the limit to which v dd can be lowered in sleep mode, or during a device reset, without losing ram data. 2: the supply current is mainly a function of the operating voltage and frequency. other factors, such as i/o pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail to rail; all i/o pins tri-stated, pulled to v dd mclr = v dd ; wdt enabled/disabled as specified. 3: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in hi-impedance state and tied to v dd or v ss , and all features that add delta current disabled (such as wdt, timer1 oscillator, bor, ...). 4: for rc osc option, current through r ext is not included. the current through the resistor can be estimated by the formula ir = v dd /2r ext (ma) with r ext in kohm.
? 2001 microchip technology inc. advance information ds39541a-page 269 PIC18C601/801 d020 i pd power-down current (3) pic18lc601/801 ? ? ? tbd ? ? 5 36 tbd a a a v dd = 2.5v, -40 c to +85 c v dd = 5.5v, -40 c to +85 c v dd = 2.5v, 25 c d020 PIC18C601/801 ? ? tbd ? tbd 36 a a v dd = 4.2v, -40 c to +85 c v dd = 5.5v, -40 c to +85 c d020a ? ? tbd a v dd = 4.2v, 25 c d021b ? ? tbd ? tbd 42 a v dd = 4.2v, -40 c to +125 c v dd = 5.5v, -40 c to +125 c d022 ? i wdt module differential current pic18lc801/601 watchdog timer ? ? ? ? tbd 6.5 ? ? tbd 12 tbd tbd a a a a v dd = 2.5v v dd = 3.0v v dd = 5.5v v dd = 2.5v, 25 c d022 PIC18C601/801 watchdog timer ? ? ? ? ? ? tbd tbd tbd a a a v dd = 5.5v, -40 c to +85 c v dd = 5.5v, -40 c to +125 c v dd = 4.2v, 25 c d022b ? i lvd pic18lc801/601 low voltage detect ? ? ? ? 50 tbd a a v dd = 2.5v v dd = 2.5v, 25 c d022b PIC18C601/801 low voltage detect ? ? ? ? ? ? tbd tbd tbd a a a v dd = 4.2v, -40 c to +85 c v dd = 4.2v, -40 c to +125 c v dd = 4.2v, 25 c d025 ? i oscb pic18lc801/601 timer1 oscillator ? ? ? ? 3 tbd a a v dd = 2.5v v dd = 2.5v, 25 c d025 PIC18C601/801 timer1 oscillator ? ? ? ? ? ? tbd tbd tbd a a a v dd = 4.2v, -40 c to +85 c v dd = 4.2v, -40 c to +125 c v dd = 4.2v, 25 c 22.1 dc characteristics (continued) pic18lc601/801 (industrial) standard operating conditions (unless otherwise stated) operating temperature -40 c t a +85 c for industrial PIC18C601/801 (industrial, extended) standard operating conditions (unless otherwise stated) operating temperature -40 c t a +85 c for industrial -40 c t a +125 c for extended param no. symbol characteristic/ device min typ max units conditions legend: rows with industrial-extended data are shaded for improved readability. note 1: this is the limit to which v dd can be lowered in sleep mode, or during a device reset, without losing ram data. 2: the supply current is mainly a function of the operating voltage and frequency. other factors, such as i/o pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail to rail; all i/o pins tri-stated, pulled to v dd mclr = v dd ; wdt enabled/disabled as specified. 3: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in hi-impedance state and tied to v dd or v ss , and all features that add delta current disabled (such as wdt, timer1 oscillator, bor, ...). 4: for rc osc option, current through r ext is not included. the current through the resistor can be estimated by the formula ir = v dd /2r ext (ma) with r ext in kohm.
PIC18C601/801 ds39541a-page 270 advance information ? 2001 microchip technology inc. 22.2 dc characteristics: pic18c801 (industrial, extended) pic18lc601/801 (industrial) dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40 c t a +85 c for industrial -40 c t a +125 c for extended param no. symbol characteristic/ device min max units conditions v il input low voltage i/o ports: d030 with ttl buffer v ss 0.15v dd vv dd < 4.5v d030a ? 0.8 v 4.5v v dd 5.5v d031 with schmitt trigger buffer rc3 and rc4 v ss v ss 0.2 v dd 0.3v dd v v d032 mclr v ss 0.2 v dd v d032a osc1 (in xt, hs and lp modes) and t1osi v ss 0.3v dd v d033 osc1(in rc mode) (1) v ss 0.2 v dd v v ih input high voltage i/o ports: d040 with ttl buffer 0.25v dd + 0.8v v dd vv dd < 4.5v d040a 2.0 v dd v4.5v v dd 5.5v d041 with schmitt trigger buffer rc3 and rc4 0.8v dd 0.7v dd v dd v dd v v d042 mclr 0.8v dd v dd v d042a osc1 (in hs and lp modes) and t1osi 0.7v dd v dd v d043 osc1 (rc mode) (1) 0.9v dd v dd v v hys hysteresis of schmitt trigger inputs d050 tbd tbd v i il input leakage current (2,3) d060 i/o ports ? 1 av ss v pin v dd , pin at hi-impedance d061 mclr ? 5 avss v pin v dd d063 osc1 ? 5 avss v pin v dd i pu weak pull-up current d070 i purb portb weak pull-up current 50 400 av dd = 5v, v pin = v ss note 1: in rc oscillator option, the osc1/clki pin is a schmitt trigger input. it is not recommended that the picmicro device be driven with an external clock while in rc mode. 2: the leakage current on the mclr pin is strongly dependent on the applied voltage level. the specified levels represent normal operating conditions. higher leakage current may be measured at different input voltages. 3: negative current is defined as current sourced by the pin.
? 2001 microchip technology inc. advance information ds39541a-page 271 PIC18C601/801 v ol output low voltage d080 i/o ports ? 0.6 v i ol = 8.5 ma, v dd = 4.5v, -40 c to +85 c d080a ? 0.6 v i ol = 7.0 ma, v dd = 4.5v, -40 c to +125 c d083 osc2/clko (rc mode) ? 0.6 v i ol = 1.6 ma, v dd = 4.5v, -40 c to +85 c d083a ? 0.6 v i ol = 1.2 ma, v dd = 4.5v, -40 c to +125 c d084 system bus mode ? tbd v i ol = 1.6 ma, v dd = 4.5v, -40 c to +85 c d084a ? tbd v i ol = 1.2 ma, v dd = 4.5v, -40 c to +125 c d085 control signals ? tbd v i ol = 1.6 ma, v dd = 4.5v, -40 c to +85 c d085a ? tbd v i ol = 1.2 ma, v dd = 4.5v, -40 c to +125 c v oh output high voltage (3) d090 i/o ports v dd - 0.7 ? vi oh = -3.0 ma, v dd = 4.5v, -40 c to +85 c d090a v dd - 0.7 ? vi oh = -2.5 ma, v dd = 4.5v, -40 c to +125 c d092 osc2/clko (rc mode) v dd - 0.7 ? vi oh = -1.3 ma, v dd = 4.5v, -40 c to +85 c d092a v dd - 0.7 ? vi oh = -1.0 ma, v dd = 4.5v, -40 c to +125 c d093 system bus mode tbd ? vi oh = -1.3 ma, v dd = 4.5v, -40 c to +85 c d093a tbd ? vi oh = -1.0 ma, v dd = 4.5v, -40 c to +125 c d094 control signals tbd ? vi oh = -1.3 ma, v dd = 4.5v, -40 c to +85 c d094a tbd ? vi oh = -1.0 ma, v dd = 4.5v, -40 c to +125 c v od open-drain high voltage d150 ? 7.5 v ra4 pin capacitive loading specs on output pins d101 c io all i/o pins and osc2 (in rc mode) ? 50 pf to meet the ac timing specifications d102 c b scl, sda ? 400 pf in i 2 c mode 22.2 dc characteristics: pic18c801 (industrial, extended) pic18lc601/801 (industrial) (continued) dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40 c t a +85 c for industrial -40 c t a +125 c for extended param no. symbol characteristic/ device min max units conditions note 1: in rc oscillator option, the osc1/clki pin is a schmitt trigger input. it is not recommended that the picmicro device be driven with an external clock while in rc mode. 2: the leakage current on the mclr pin is strongly dependent on the applied voltage level. the specified levels represent normal operating conditions. higher leakage current may be measured at different input voltages. 3: negative current is defined as current sourced by the pin.
PIC18C601/801 ds39541a-page 272 advance information ? 2001 microchip technology inc. figure 22-3: low-voltage detect characteristics table 22-1: low voltage detect characteristics v lvd lvdif v dd (lvdif set by hardware) (lvdif can be cleared in software) v cc = 2.0v to 5.5v commercial (c): t amb = 0 c to +70 c industrial (i): t amb = -40 c to +85 c param no. characteristic symbol min typ ? max units conditions d420 lvd voltage on v dd transition high to low lvv = 0001 v lvd 2.0 2.06 2.12 v lvv = 0010 2.2 2.27 2.34 v lvv = 0011 2.4 2.47 2.54 v lvv = 0100 2.5 2.58 2.66 v lvv = 0101 2.7 2.78 2.86 v lvv = 0110 2.8 2.89 2.98 v lvv = 0111 3.0 3.1 3.2 v lvv = 1000 3.3 3.41 3.52 v lvv = 1001 3.5 3.61 3.72 v lvv = 1010 3.6 3.72 3.84 v lvv = 1011 3.8 3.92 4.04 v lvv = 1100 4.0 4.13 4.26 v lvv = 1101 4.2 4.33 4.46 v lvv = 1110 4.5 4.64 4.78 v d421 lvd voltage drift temperature coefficient tcv out ? 15 50 ppm/ c d422 bandgap voltage drift with respect to v dd regulation ? v bg / ? v dd ?? 50 v/v d423 bandgap reference voltage value v bg ? 1.22 v note: production tested at t amb = 25 c. specifications over temperature limits guaranteed by characterization.
? 2001 microchip technology inc. advance information ds39541a-page 273 PIC18C601/801 22.3 ac (timing) characteristics 22.3.1 timing parameter symbology the timing parameter symbols have been created following one of the following formats: 1. tpps2pps 3. t cc : st (i 2 c specifications only) 2. tpps 4. ts (i 2 c specifications only) t f frequency t time lowercase letters (pp) and their meanings: pp cc ccp1 osc osc1 ck clko rd rd cs cs rw rd or wr di sdi sc sck do sdo ss ss dt data-in t0 t0cki io i/o port t1 t1cki mc mclr wr wr uppercase letters and their meanings: s ffall pperiod hhigh rrise i invalid (hi-impedance) v valid l low z hi-impedance i 2 c only aa output access high high buf bus free low low t cc : st (i 2 c specifications only) cc hd hold su setup st dat data input hold sto stop condition sta start condition
PIC18C601/801 ds39541a-page 274 advance information ? 2001 microchip technology inc. 22.3.2 timing conditions the temperature and voltages specified in table 22-2 apply to all timing specifications, unless otherwise noted. figure 22-4 specifies the load conditions for the timing specifications. table 22-2: temperature and voltage specifications - ac figure 22-4: load conditions for device timing specifications ac characteristics standard operating conditions (unless otherwise stated) operating temperature -40 c t a +85 c for industrial -40 c t a +125 c for extended operating voltage v dd range as described in dc spec section 22.1. lc parts operate for industrial temperatures only. v dd /2 c l r l pin pin v ss v ss c l r l =464 ? c l = 50 pf for all pins except osc2/clko and including d and e outputs as ports load condition 1 load condition 2
? 2001 microchip technology inc. advance information ds39541a-page 275 PIC18C601/801 22.3.3 timing diagrams and specifications figure 22-5: external clock timing table 22-3: external clock timing requirements table 22-4: pll clock timing specification (v dd = 4.2v - 5.5v) osc1 clkout q4 q1 q2 q3 q4 q1 1 2 3 3 4 4 param no. symbol characteristic min typ max units f osc external clki frequency (note 1) dc ? 4mhz dc ? 25 mhz 4 ? 6.25 mhz dc ? 25 mhz dc ? 200 khz oscillator frequency (note 1) dc ? 4mhz 4 ? 25 mhz 4 ? 6.25 mhz 5 ? 200 khz 1tosc external clki period (note 1) 250 ?? ns 40 ?? ns 40 ?? ns 160 ?? ns 5 ?? s oscillator period (note 1) 250 ?? ns 40 ? 100 ns 160 ? 100 ns 5 ?? s 2t cy instruction cycle time (note 1) 160 t cy dc ns 3 tosl, to s h external clock in (osc1) high or low time 2.5 ?? s 10 ?? ns 4tosr, tos f external clock in (osc1) rise or fall time ? ? 50 ns ?? 5ns note 1: instruction cycle period (t cy ) equals four times the input oscillator time-base period. all specified values are based on characterization data for that particular oscillator type under standard operating conditions, with the device exe- cuting code. exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. all devices are tested to operate at "min." values with an external clock applied to the osc1/clki pin. when an external clock input is used, the "max." cycle time limit is "dc" (no clock) for all devices. param no. symbol characteristic min max units conditions 7t pll pll start-up time (lock time) ? 2ms ? clk clkout stability (jitter) using pll -2 +2 %
PIC18C601/801 ds39541a-page 276 advance information ? 2001 microchip technology inc. figure 22-6: clkout and i/o timing table 22-5: clkout and i/o timing requirements note: refer to figure 22-4 for load conditions. osc1 clkout i/o pin (input) i/o pin (output) q4 q1 q2 q3 10 13 14 17 20, 21 19 18 15 11 12 16 old value new value param. no. symbol characteristic min typ max units conditions 10 tosh2ckl osc1 to clkout ? 75 200 ns (1) 11 tosh2ckh osc1 to clkout ? 75 200 ns (1) 12 tckr clkout rise time ? 35 100 ns (1) 13 tckf clkout fall time ? 35 100 ns (1) 14 tckl2iov clkout to port out valid ?? 0.5t cy + 20 ns (1) 15 tiov2ckh port in valid before clkout 0.25t cy + 25 ?? ns (1) 16 tckh2ioi port in hold after clkout 0 ?? ns (1) 17 tosh2iov osc1 (q1 cycle) to port out valid ? 50 150 ns 18 tosh2ioi osc1 (q2 cycle) to port input invalid (i/o in hold time) PIC18C601/801 100 ?? ns 18a pic18 lc 601/801 200 ?? ns 19 tiov2osh port input valid to osc1 (i/o in setup time) 0 ?? ns 20 tior port output rise time PIC18C601/801 ? 10 25 ns 20a pic18 lc 601/801 ?? 60 ns 21 tiof port output fall time PIC18C601/801 ? 10 25 ns 21a pic18 lc 601/801 ?? 60 ns 22 ?? t inp int pin high or low time t cy ?? ns 23 ?? t rbp rb7:rb4 change int high or low time t cy ?? ns ?? these parameters are asynchronous events, not related to any internal clock edges. note 1: measurements are taken in rc mode, where clko pin output is 4 x t osc .
? 2001 microchip technology inc. advance information ds39541a-page 277 PIC18C601/801 figure 22-7: program memory read timing diagram operating conditions: 2.0v 167 168 155 address address 150 a<19:16> address 169 ba0 cs1 cs2 or csio 171 171a
PIC18C601/801 ds39541a-page 278 advance information ? 2001 microchip technology inc. figure 22-8: 8-bit program memory fetch timing diagram operating conditions: 2.0v address address a<19:8> address 162a ba0 data 170a cs1 cs2 or csio 151 150 166
? 2001 microchip technology inc. advance information ds39541a-page 279 PIC18C601/801 figure 22-9: program memory write timing diagram operating conditions: 2.0v address wrh or wrl ub or lb 157 154 157a address a<19:16> address ba0 cs1 , cs2 , or csio 166
PIC18C601/801 ds39541a-page 280 advance information ? 2001 microchip technology inc. figure 22-10: reset, watchdog timer, oscillator start-up timer and power-up timer timing table 22-9: reset, watchdog timer, oscillator start-up timer, power-up timer and brown-out reset requirements v dd mclr internal por pwrt time-out osc time-out internal reset watchdog timer reset 33 32 30 31 34 i/o pins 34 note: refer to figure 22-4 for load conditions. param. no. symbol characteristic min typ max units conditions 30 tmcl mclr pulse width (low) 2 ?? s 31 t wdt watchdog timer time-out period (no prescaler) 71833ms 32 t ost oscillation start-up timer period ?? 1024t osc ? t osc = osc1 period 33 t pwrt power up timer period 28 72 132 ms 34 t ioz i/o hi-impedance from mclr low or watchdog timer reset ? 2 ? s
? 2001 microchip technology inc. advance information ds39541a-page 281 PIC18C601/801 figure 22-11: timer0 and timer1 external clock timings table 22-10: timer0 and timer1 external clock requirements note: refer to figure 22-4 for load conditions. 46 47 45 48 41 42 40 t0cki t1oso/t1cki tmr0 or tmr1 param no. symbol characteristic min max units conditions 40 tt0h t0cki high pulse width no prescaler 0.5t cy + 20 ? ns with prescaler 10 ? ns 41 tt0l t0cki low pulse width no prescaler 0.5t cy + 20 ? ns with prescaler 10 ? ns 42 tt0p t0cki period no prescaler t cy + 10 ? ns with prescaler greater of: 20 n s or t cy + 40 n ? ns n = prescale value (1, 2, 4,..., 256) 45 tt1h t1cki high time synchronous, no prescaler 0.5t cy + 20 ? ns synchronous, with prescaler PIC18C601/801 10 ? ns pic18 lc 601/801 25 ? ns asynchronous PIC18C601/801 30 ? ns pic18 lc 601/801 50 ? ns 46 tt1l t1cki low time synchronous, no prescaler 0.5t cy + 5 ? ns synchronous, with prescaler PIC18C601/801 10 ? ns pic18 lc 601/801 25 ? ns asynchronous PIC18C601/801 30 ? ns pic18 lc 601/801 tbd tbd ns 47 tt1p t1cki input period synchronous greater of: 20 n s or t cy + 40 n ? ns n = prescale value (1, 2, 4, 8) asynchronous 60 ? ns ft1 t1cki oscillator input frequency range dc 50 khz 48 tcke2tmri delay from external t1cki clock edge to timer increment 2t osc 7t osc ?
PIC18C601/801 ds39541a-page 282 advance information ? 2001 microchip technology inc. figure 22-12: capture/compare/pwm timings (ccp1 and ccp2) table 22-11: capture/compare/pwm requirements (ccp1 and ccp2) note: refer to figure 22-4 for load conditions. ccpx (capture mode) 50 51 52 ccpx 53 54 (compare or pwm mode) param. no. symbol characteristic min max units conditions 50 tccl ccpx input low time no prescaler 0.5t cy + 20 ? ns with prescaler pic18 c 601/801 10 ? ns pic18 lc 601/801 20 ? ns 51 tcch ccpx input high time no prescaler 0.5t cy + 20 ? ns with prescaler pic18 c 601/801 10 ? ns pic18 lc 601/801 20 ? ns 52 tccp ccpx input period 3t cy + 40 n ? ns n = prescale value (1, 4 or 16) 53 tccr ccpx output fall time pic18 c 601/801 ? 25 ns pic18 lc 601/801 ? 45 ns 54 tccf ccpx output fall time pic18 c 601/801 ? 25 ns pic18 lc 601/801 ? 45 ns
? 2001 microchip technology inc. advance information ds39541a-page 283 PIC18C601/801 figure 22-13: example spi master mode timing (cke = 0) table 22-12: example spi mode requirements (master mode, cke = 0) ss sck (ckp = 0) sck (ckp = 1) sdo sdi 70 71 72 73 74 75, 76 78 79 80 79 78 msb lsb bit6 - - - - - -1 msb in lsb in bit6 - - - -1 note: refer to figure 22-4 for load conditions. param. no. symbol characteristic min max units conditions 70 tssl2sch, tssl2scl ss to sck or sck input t cy ? ns 71 tsch sck input high time (slave mode) continuous 1.25t cy + 30 ? ns 71a single byte 40 ? ns (note 1) 72 tscl sck input low time (slave mode) continuous 1.25t cy + 30 ? ns 72a single byte 40 ? ns (note 1) 73 tdiv2sch, tdiv2scl setup time of sdi data input to sck edge 100 ? ns 73a t b 2 b last clock edge of byte1 to the 1st clock edge of byte2 1.5t cy + 40 ? ns (note 2) 74 tsch2dil, ts c l 2 d i l hold time of sdi data input to sck edge 100 ? ns 75 tdor sdo data output rise time pic18 c 601/801 ? 25 ns pic18 lc 601/801 ? 45 ns 76 tdof sdo data output fall time ? 25 ns 78 tscr sck output rise time (master mode) pic18 c 601/801 ? 25 ns pic18 lc 601/801 ? 45 ns 79 tscf sck output fall time (master mode) ? 25 ns 80 tsch2dov, tscl2dov sdo data output valid after sck edge pic18 c 601/801 ? 50 ns pic18 lc 601/801 ? 100 ns note 1: requires the use of parameter # 73a. 2: only if parameter #s 71a and 72a are used.
PIC18C601/801 ds39541a-page 284 advance information ? 2001 microchip technology inc. figure 22-14: example spi master mode timing (cke = 1) table 22-13: example spi mode requirements (master mode, cke = 1) ss sck (ckp = 0) sck (ckp = 1) sdo sdi 81 71 72 74 75, 76 78 80 msb 79 73 msb in bit6 - - - - - -1 lsb in bit6 - - - -1 lsb note: refer to figure 22-4 for load conditions. param. no. symbol characteristic min max units conditions 71 tsch sck input high time (slave mode) continuous 1.25t cy + 30 ? ns 71a single byte 40 ? ns (note 1) 72 tscl sck input low time (slave mode) continuous 1.25t cy + 30 ? ns 72a single byte 40 ? ns (note 1) 73 tdiv2sch, tdiv2scl setup time of sdi data input to sck edge 100 ? ns 73a t b 2 b last clock edge of byte1 to the 1st clock edge of byte2 1.5t cy + 40 ? ns (note 2) 74 tsch2dil, ts c l 2 d i l hold time of sdi data input to sck edge 100 ? ns 75 tdor sdo data output rise time pic18 c 601/801 ? 25 ns pic18 lc 601/801 ? 45 ns 76 tdof sdo data output fall time ? 25 ns 78 tscr sck output rise time (master mode) pic18 c 601/801 ? 25 ns pic18 lc 601/801 ? 45 ns 79 tscf sck output fall time (master mode) ? 25 ns 80 tsch2dov, tscl2dov sdo data output valid after sck edge pic18 c 601/801 ? 50 ns pic18 lc 601/801 ? 100 ns 81 tdov2sch, tdov2scl sdo data output setup to sck edge t cy ? ns note 1: requires the use of parameter # 73a. 2: only if parameter #s 71a and 72a are used.
? 2001 microchip technology inc. advance information ds39541a-page 285 PIC18C601/801 figure 22-15: example spi slave mode timing (cke = 0) ss sck (ckp = 0) sck (ckp = 1) sdo sdi 70 71 72 73 74 75, 76 77 78 79 80 79 78 sdi msb lsb bit6 - - - - - -1 msb in bit6 - - - -1 lsb in 83 note: refer to figure 22-4 for load conditions. table 22-14: example spi mode requirements (slave mode timing (cke = 0)) param no. symbol characteristic min max units conditions 70 tssl2sch, tssl2scl ss to sck or sck input t cy ? ns 71 tsch sck input high time (slave mode) continuous 1.25t cy + 30 ? ns 71a single byte 40 ? ns (note 1) 72 tscl sck input low time (slave mode) continuous 1.25t cy + 30 ? ns 72a single byte 40 ? ns (note 1) 73 tdiv2sch, tdiv2scl setup time of sdi data input to sck edge 100 ? ns 73a t b 2 b last clock edge of byte1 to the 1st clock edge of byte2 1.5t cy + 40 ? ns (note 2) 74 tsch2dil, tscl2dil hold time of sdi data input to sck edge 100 ? ns 75 tdor sdo data output rise time pic18 c 601/801 ? 25 ns pic18 lc 601/801 45 ns 76 tdof sdo data output fall time ? 25 ns 77 tssh2doz ss to sdo output hi-impedance 10 50 ns 78 tscr sck output rise time (master mode) pic18 c 601/801 ? 25 ns pic18 lc 601/801 45 ns 79 tscf sck output fall time (master mode) ? 25 ns 80 tsch2dov, tscl2dov sdo data output valid after sck edge pic18 c 601/801 ? 50 ns pic18 lc 601/801 100 ns 83 tsch2ssh, tscl2ssh ss after sck edge 1.5t cy + 40 ? ns note 1: requires the use of parameter # 73a. 2: only if parameter #s 71a and 72a are used.
PIC18C601/801 ds39541a-page 286 advance information ? 2001 microchip technology inc. figure 22-16: example spi slave mode timing (cke = 1) ss sck (ckp = 0) sck (ckp = 1) sdo sdi 70 71 72 82 sdi 74 75, 76 msb bit6 - - - - - -1 lsb 77 msb in bit6 - - - -1 lsb in 80 83 note: refer to figure 22-4 for load conditions. table 22-15: example spi slave mode requirements (cke = 1) param no. symbol characteristic min max units conditions 70 tssl2sch, tssl2scl ss to sck or sck input t cy ? ns 71 tsch sck input high time (slave mode) continuous 1.25t cy + 30 ? ns 71a single byte 40 ? ns (note 1) 72 tscl sck input low time (slave mode) continuous 1.25t cy + 30 ? ns 72a single byte 40 ? ns (note 1) 73a t b 2 b last clock edge of byte1 to the 1st clock edge of byte2 1.5t cy + 40 ? ns (note 2) 74 tsch2dil, tscl2dil hold time of sdi data input to sck edge 100 ? ns 75 tdor sdo data output rise time pic18 c 601/801 ? 25 ns pic18 lc 601/801 ? 45 ns 76 tdof sdo data output fall time ? 25 ns 77 tssh2doz ss to sdo output hi-impedance 10 50 ns 78 tscr sck output rise time (master mode) pic18 c 601/801 ? 25 ns pic18 lc 601/801 ? 45 ns 79 tscf sck output fall time (master mode) ? 25 ns 80 tsch2dov, tscl2dov sdo data output valid after sck edge pic18 c 601/801 ? 50 ns pic18 lc 601/801 ? 100 ns 82 tssl2dov sdo data output valid after ss edge pic18 c 601/801 ? 50 ns pic18 lc 601/901 ? 100 ns 83 tsch2ssh, tscl2ssh ss after sck edge 1.5t cy + 40 ? ns note 1: requires the use of parameter # 73a. 2: only if parameter #s 71a and 72a are used.
? 2001 microchip technology inc. advance information ds39541a-page 287 PIC18C601/801 figure 22-17: i 2 c bus start/stop bits timing table 22-16: i 2 c bus start/stop bits requirements (slave mode) figure 22-18: i 2 c bus data timing note: refer to figure 22-4 for load conditions. 91 92 93 scl sda start condition stop condition 90 param. no. symbol characteristic min max units conditions 90 t su : sta start condition 100 khz mode 4700 ? ns only relevant for repeated start condition setup time 400 khz mode 600 ? 91 t hd : sta start condition 100 khz mode 4000 ? ns after this period, the first clock pulse is generated hold time 400 khz mode 600 ? 92 t su : sto stop condition 100 khz mode 4700 ? ns setup time 400 khz mode 600 ? 93 t hd : sto stop condition 100 khz mode 4000 ? ns hold time 400 khz mode 600 ? note: refer to figure 22-4 for load conditions. 90 91 92 100 101 103 106 107 109 109 110 102 scl sda in sda out
PIC18C601/801 ds39541a-page 288 advance information ? 2001 microchip technology inc. table 22-17: i 2 c bus data requirements (slave mode) param no. symbol characteristic min max units conditions 100 t high clock high time 100 khz mode 4.0 ? s PIC18C601/801 must operate at a minimum of 1.5 mhz 400 khz mode 0.6 ? s PIC18C601/801 must operate at a minimum of 10 mhz ssp module 1.5t cy ? 101 t low clock low time 100 khz mode 4.7 ? s PIC18C601/801 must operate at a minimum of 1.5 mhz 400 khz mode 1.3 ? s PIC18C601/801 must operate at a minimum of 10 mhz ssp module 1.5t cy ? ns 102 t r sda and scl rise time 100 khz mode ? 1000 ns 400 khz mode 20 + 0.1cb 300 ns cb is specified to be from 10 to 400 pf 103 t f sda and scl fall time 100 khz mode ? 300 ns 400 khz mode 20 + 0.1cb 300 ns cb is specified to be from 10 to 400 pf 90 t su : sta start condition setup time 100 khz mode 4.7 ? s only relevant for repeated start condition 400 khz mode 0.6 ? s 91 t hd : sta start condition hold time 100 khz mode 4.0 ? s after this period the first clock pulse is generated 400 khz mode 0.6 ? s 106 t hd : dat data input hold time 100 khz mode 0 ? ns 400 khz mode 0 0.9 s 107 t su : dat data input setup time 100 khz mode 250 ? ns (note 2) 400 khz mode 100 ? ns 92 t su : sto stop condition setup time 100 khz mode 4.7 ? s 400 khz mode 0.6 ? s 109 t aa output valid from clock 100 khz mode ? 3500 ns (note 1) 400 khz mode ?? ns 110 t buf bus free time 100 khz mode 4.7 ? s time the bus must be free before a new transmission can start 400 khz mode 1.3 ? s d102 cb bus capacitive loading ? 400 pf note 1: as a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of scl to avoid unintended generation of start or stop conditions. 2: a fast mode i 2 c bus device can be used in a standard mode i 2 c bus system, but the requirement tsu;dat 250 ns must then be met. this will automatically be the case if the device does not stretch the low period of the scl signal. if such a device does stretch the low period of the scl signal, it must output the next data bit to the sda line. before the scl line is released, t r max. + tsu;dat = 1000 + 250 = 1250 ns (according to the standard mode i 2 c bus specification).
? 2001 microchip technology inc. advance information ds39541a-page 289 PIC18C601/801 figure 22-19: master ssp i 2 c bus start/stop bits timing waveforms table 22-18: master ssp i 2 c bus start/stop bits requirements figure 22-20: master ssp i 2 c bus data timing note: refer to figure 22-4 for load conditions. 91 93 scl sda start condition stop condition 90 92 param. no. symbol characteristic min max units conditions 90 t su : sta start condition 100 khz mode 2(t osc )(brg + 1) ? ns only relevant for repeated start condition setup time 400 khz mode 2(t osc )(brg + 1) ? 1 mhz mode (1) 2(t osc )(brg + 1) ? 91 t hd : sta start condition 100 khz mode 2(t osc )(brg + 1) ? ns after this period, the first clock pulse is generated hold time 400 khz mode 2(t osc )(brg + 1) ? 1 mhz mode (1) 2(t osc )(brg + 1) ? 92 t su : sto stop condition 100 khz mode 2(t osc )(brg + 1) ? ns setup time 400 khz mode 2(t osc )(brg + 1) ? 1 mhz mode (1) 2(t osc )(brg + 1) ? 93 t hd : sto stop condition 100 khz mode 2(t osc )(brg + 1) ? ns hold time 400 khz mode 2(t osc )(brg + 1) ? 1 mhz mode (1) 2(t osc )(brg + 1) ? note 1: maximum pin capacitance = 10 pf for all i 2 c pins. note: refer to figure 22-4 for load conditions. 90 91 92 100 101 103 106 107 109 109 110 102 scl sda in sda out
PIC18C601/801 ds39541a-page 290 advance information ? 2001 microchip technology inc. table 22-19: master ssp i 2 c bus data requirements param no. symbol characteristic min max units conditions 100 t high clock high time 100 khz mode 2(t osc )(brg + 1) ? ms 400 khz mode 2(t osc )(brg + 1) ? ms 1 mhz mode (1) 2(t osc )(brg + 1) ? ms 101 t low clock low time 100 khz mode 2(t osc )(brg + 1) ? ms 400 khz mode 2(t osc )(brg + 1) ? ms 1 mhz mode (1) 2(t osc )(brg + 1) ? ms 102 t r sda and scl rise time 100 khz mode ? 1000 ns cb is specified to be from 10 to 400 pf 400 khz mode 20 + 0.1cb 300 ns 1 mhz mode (1) ? 300 ns 103 t f sda and scl fall time 100 khz mode ? 300 ns cb is specified to be from 10 to 400 pf 400 khz mode 20 + 0.1cb 300 ns 1 mhz mode (1) ? 100 ns 90 t su : sta start condition setup time 100 khz mode 2(t osc )(brg + 1) ? ms only relevant for repeated start condition 400 khz mode 2(t osc )(brg + 1) ? ms 1 mhz mode (1) 2(t osc )(brg + 1) ? ms 91 t hd : sta start condition hold time 100 khz mode 2(t osc )(brg + 1) ? ms after this period, the first clock pulse is generated 400 khz mode 2(t osc )(brg + 1) ? ms 1 mhz mode (1) 2(t osc )(brg + 1) ? ms 106 t hd : dat data input hold time 100 khz mode 0 ? ns 400 khz mode 0 0.9 ms 1 mhz mode (1) tbd ? ns 107 t su : dat data input setup time 100 khz mode 250 ? ns (note 2) 400 khz mode 100 ? ns 1 mhz mode (1) tbd ? ns 92 t su : sto stop condition setup time 100 khz mode 2(t osc )(brg + 1) ? ms 400 khz mode 2(t osc )(brg + 1) ? ms 1 mhz mode (1) 2(t osc )(brg + 1) ? ms 109 t aa output valid from clock 100 khz mode ? 3500 ns 400 khz mode ? 1000 ns 1 mhz mode (1) ?? ns 110 t buf bus free time 100 khz mode 4.7 ? ms time the bus must be free before a new transmission can start 400 khz mode 1.3 ? ms 1 mhz mode (1) tbd ? ms d102 cb bus capacitive loading ? 400 pf note 1: maximum pin capacitance = 10 pf for all i 2 c pins. 2: a fast mode i 2 c bus device can be used in a standard mode i 2 c bus system, but parameter #107 250 ns must then be met. this will automatically be the case if the device does not stretch the low period of the scl signal. if such a device does stretch the low period of the scl signal, it must output the next data bit to the sda line. before the scl line is released, parameter #102 + parameter #107 = 1000 + 250 = 1250 ns (for 100 khz mode).
? 2001 microchip technology inc. advance information ds39541a-page 291 PIC18C601/801 figure 22-21: usart synchronous transmission (master/slave) timing table 22-20: usart synchronous transmission requirements figure 22-22: usart synchronous receive (master/slave) timing table 22-21: usart synchronous receive requirements note: refer to figure 22-4 for load conditions. 121 121 120 122 rc6/tx/ck rc7/rx/dt pin pin param no. symbol characteristic min max units conditions 120 tckh2dtv sync xmit (m aster & s lave ) clock high to data-out valid pic18 c 601/801 ? 40 ns pic18 lc 601/801 ? 100 ns 121 tckrf clock out rise time and fall time (master mode) pic18 c 601/801 ? 20 ns pic18 lc 601/801 ? 50 ns 122 tdtrf data-out rise time and fall time pic18 c 601/801 ? 20 ns pic18 lc 601/801 ? 50 ns note: refer to figure 22-4 for load conditions. 125 126 rc6/tx/ck rc7/rx/dt pin pin param no. symbol characteristic min max units conditions 125 tdtv2ckl sync rcv (m aster & s lave ) data-hold before ck (dt hold time) 10 ? ns 126 tckl2dtl data-hold after ck (dt hold time) 15 ? ns
PIC18C601/801 ds39541a-page 292 advance information ? 2001 microchip technology inc. table 22-22: a/d converter characteristics: PIC18C601/801 (industrial, extended) pic18lc601/801 (industrial) param no. symbol characteristic min typ max units conditions a01 n r resolution ? ? ? ? 10 tbd bit bit v ref = v dd 3.0v v ref = v dd < 3.0v a03 e il integral linearity error ? ? ? ? <1 tbd lsb lsb v ref = v dd 3.0v v ref = v dd < 3.0v a04 e dl differential linearity error ? ? ? ? <1 tbd lsb lsb v ref = v dd 3.0v v ref = v dd < 3.0v a05 e fs full scale error ? ? ? ? <1 tbd lsb lsb v ref = v dd 3.0v v ref = v dd < 3.0v a06 e off offset error ? ? ? ? <1 tbd lsb lsb v ref = v dd 3.0v v ref = v dd < 3.0v a10 ? monotonicity guaranteed ( 3 ) ? v ss v ain v ref a20 v ref reference voltage (v refh - v refl ) 0 ?? v a20a 3 ?? v for 10-bit resolution a21 v refh reference voltage high av ss ? av dd + 0.3 v v a22 v refl reference voltage low av ss - 0.3 v ? av dd v a25 v ain analog input voltage av ss - 0.3 v ? v ref + 0.3 v v a30 z ain recommended impedance of analog voltage source ?? 10.0 k ? a40 i ad a/d conversion current (v dd ) pic18 c 601/801 ? 180 ? a average current consumption when a/d is on (1) pic18l c 601/801 ? 90 ? a a50 i ref v ref input current (2) 10 ? ? ? 1000 10 a a during v ain acquisition. based on differential of v hold to v ain . to charge c hold , see section 17.0. during a/d conversion cycle. note 1: when a/d is off, it will not consume any current other than minor leakage current. the power-down current spec includes any such leakage from the a/d module. v ref current is from ra2/an2/v ref - and ra3/an3/v ref + pins or av dd and av ss pins, whichever is selected as reference input. 2: vss v ain v ref 3: the a/d conversion result either increases or remains constant as the analog input increases.
? 2001 microchip technology inc. advance information ds39541a-page 293 PIC18C601/801 figure 22-23: a/d conversion timing table 22-23: a/d conversion requirements param no. symbol characteristic min max units conditions 130 t ad a/d clock period pic18 c 601/801 1.6 20 (5) st osc based, v ref 3.0v pic18 lc 601/801 3.0 20 (5) st osc based, v ref full range pic18 c 601/801 2.0 6.0 sa/d rc mode pic18 lc 601/801 3.0 9.0 sa/d rc mode 131 t cnv conversion time (not including acquisition time) (1) 11 12 t ad 132 t acq acquisition time (3) 15 10 ? ? s s -40 c te m p 125 c 0 c te m p 125 c 135 t swc switching time from convert sample ? (note 4) 136 t amp amplifier settling time (2) 1 ? s this may be used if the ? new ? input voltage has not changed by more than 1 lsb (i.e., 5 mv @ 5.12v) from the last sampled voltage (as stated on c hold ). note 1: adres register may be read on the following t cy cycle. 2: see section 17.0 for minimum conditions, when input voltage has changed more than 1 lsb. 3: the time for the holding capacitor to acquire the ? new ? input voltage, when the voltage changes full scale after the conversion (av dd to av ss , or av ss to av dd ). the source impedance ( r s ) on the input channels is 50 ? . 4: on the next q4 cycle of the device clock. 5: the time of the a/d clock period is dependent on the device frequency and the t ad clock divider. 131 130 132 bsf adcon0, go q4 a/d clk a/d data adres adif go sample old_data sampling stopped done new_data (note 2) 987 21 0 note 1: if the a/d clock source is selected as rc, a time of t cy is added before the a/d clock starts.this allows the sleep instruction to be executed. 2: this is a minimal rc delay (typically 100 ns), which also disconnects the holding capacitor from the analog input. . . . . . . t cy
PIC18C601/801 ds39541a-page 294 advance information ? 2001 microchip technology inc. notes:
? 2001 microchip technology inc. advance information ds39541a-page 295 PIC18C601/801 23.0 dc and ac characteristics graphs and tables graphs and tables are not available at this time.
PIC18C601/801 ds39541a-page 296 advance information ? 2001 microchip technology inc. notes:
? 2001 microchip technology inc. advance information ds39541a-page 297 PIC18C601/801 24.0 packaging information 24.1 package marking information 68-lead plcc example 64-lead tqfp example 80-lead tqfp example xxxxxxxxxx yywwnnn xxxxxxxxxx xxxxxxxxxx 0017017 PIC18C601-i/pt xxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxx yywwnnn PIC18C601-i/l 0017017 xxxxxxxxxxxx yywwnnn xxxxxxxxxxxx 0017017 pic18c801-i/pt legend: xx...x customer specific information* yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ? 01 ? ) nnn alphanumeric traceability code note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information. * standard otp marking consists of microchip part number, year code, week code, facility code, mask rev#, and assembly code. for otp marking beyond this, certain price adders apply. please check with your microchip sales office. for qtp devices, any special marking adders are included in qtp price.
PIC18C601/801 ds39541a-page 298 advance information ? 2001 microchip technology inc. package marking information (cont ? d) 84-lead plcc example xxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxx yywwnnn pic18c801-i/l 0017017
? 2001 microchip technology inc. advance information ds39541a-page 299 PIC18C601/801 64-lead plastic thin quad flatpack (pt) 10x10x1 mm body, 1.0/0.10 mm lead form (tqfp) * controlling parameter notes: dimensions d1 and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010 ? (0.254mm) per side. jedec equivalent: ms-026 drawing no. c04-085 15 10 5 15 10 5 mold draft angle bottom 15 10 5 15 10 5 mold draft angle top 0.27 0.22 0.17 .011 .009 .007 b lead width 0.23 0.18 0.13 .009 .007 .005 c lead thickness 16 16 n1 pins per side 10.10 10.00 9.90 .398 .394 .390 d1 molded package length 10.10 10.00 9.90 .398 .394 .390 e1 molded package width 12.25 12.00 11.75 .482 .472 .463 d overall length 12.25 12.00 11.75 .482 .472 .463 e overall width 7 3.5 0 7 3.5 0 foot angle 0.75 0.60 0.45 .030 .024 .018 l foot length 0.25 0.15 0.05 .010 .006 .002 a1 standoff 1.05 1.00 0.95 .041 .039 .037 a2 molded package thickness 1.20 1.10 1.00 .047 .043 .039 a overall height 0.50 .020 p pitch 64 64 n number of pins max nom min max nom min dimension limits millimeters* inches units c 2 1 n d d1 b p #leads=n1 e1 e a2 a1 a l ch x 45 (f) footprint (reference) (f) .039 1.00 pin 1 corner chamfer ch .025 .035 .045 0.64 0.89 1.14 significant characteristic
PIC18C601/801 ds39541a-page 300 advance information ? 2001 microchip technology inc. 68-lead plastic leaded chip carrier (l) ? square (plcc) 10 5 0 10 5 0 mold draft angle bottom 10 5 0 10 5 0 mold draft angle top 0.53 0.51 0.33 .021 .020 .013 b lower lead width 0.81 0.74 0.66 .032 .029 .026 b1 upper lead width 0.33 0.27 0.20 .013 .011 .008 c lead thickness 17 17 n1 pins per side 23.62 23.37 22.61 .930 .920 .890 d2 footprint length 23.62 23.37 22.61 .930 .920 .890 e2 footprint width 24.33 24.23 24.13 .958 .954 .950 d1 molded package length 24.33 24.23 24.13 .958 .954 .950 e1 molded package width 25.27 25.15 25.02 .995 .990 .985 d overall length 25.27 25.15 25.02 .995 .990 .985 e overall width 0.25 0.13 0.00 .010 .005 .000 ch2 corner chamfer (others) 1.27 1.14 1.02 .050 .045 .040 ch1 corner chamfer 1 0.86 0.74 0.61 .034 .029 .024 a3 side 1 chamfer height 0.51 .020 a1 standoff a2 molded package thickness 4.57 4.39 4.19 .180 .173 .165 a overall height 1.27 .050 p pitch 68 n number of pins max nom min max nom min dimension limits millimeters inches* units a2 c e2 2 d d1 n #leads=n1 e e1 1 p b a3 a b1 32 d2 68 a1 .145 .153 .160 3.68 3.87 4.06 .028 .035 0.71 0.89 ch1 x 45 ch2 x 45 * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010 ? (0.254mm) per side. jedec equivalent: mo-047 drawing no. c04-049 significant characteristic
? 2001 microchip technology inc. advance information ds39541a-page 301 PIC18C601/801 80-lead plastic thin quad flatpack (pt) 12x12x1 mm body, 1.0/0.10 mm lead form (tqfp) * controlling parameter notes: dimensions d1 and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010 ? (0.254mm) per side. jedec equivalent: ms-026 drawing no. c04-092 1.10 1.00 .043 .039 1.14 0.89 0.64 .045 .035 .025 ch pin 1 corner chamfer 1.00 .039 (f) footprint (reference) (f) e e1 #leads=n1 p b d1 d n 1 2 c l a a1 a2 units inches millimeters* dimension limits min nom max min nom max number of pins n 80 80 pitch p .020 0.50 overall height a .047 1.20 molded package thickness a2 .037 .039 .041 0.95 1.00 1.05 standoff a1 .002 .004 .006 0.05 0.10 0.15 foot length l .018 .024 .030 0.45 0.60 0.75 foot angle 03.5 7 03.5 7 overall width e .541 .551 .561 13.75 14.00 14.25 overall length d .541 .551 .561 13.75 14.00 14.25 molded package width e1 .463 .472 .482 11.75 12.00 12.25 molded package length d1 .463 .472 .482 11.75 12.00 12.25 pins per side n1 20 20 lead thickness c .004 .006 .008 0.09 0.15 0.20 lead width b .007 .009 .011 0.17 0.22 0.27 mold draft angle top 5 10 15 5 10 15 mold draft angle bottom 5 10 15 5 10 15 ch x 45 significant characteristic
PIC18C601/801 ds39541a-page 302 advance information ? 2001 microchip technology inc. 84-lead plastic leaded chip carrier (l) ? square (plcc) 10 5 0 10 5 0 mold draft angle bottom 10 5 0 10 5 0 mold draft angle top 0.53 0.51 0.33 .021 .020 .013 b lower lead width 0.81 0.74 0.66 .032 .029 .026 b1 upper lead width 0.33 0.27 0.20 .013 .011 .008 c lead thickness 17 17 n1 pins per side 23.62 23.37 22.61 .930 .920 .890 d2 footprint length 23.62 23.37 22.61 .930 .920 .890 e2 footprint width 24.33 24.23 24.13 .958 .954 .950 d1 molded package length 24.33 24.23 24.13 .958 .954 .950 e1 molded package width 25.27 25.15 25.02 .995 .990 .985 d overall length 25.27 25.15 25.02 .995 .990 .985 e overall width 0.25 0.13 0.00 .010 .005 .000 ch2 corner chamfer (others) 1.27 1.14 1.02 .050 .045 .040 ch1 corner chamfer 1 0.86 0.74 0.61 .034 .029 .024 a3 side 1 chamfer height 0.51 .020 a1 standoff a2 molded package thickness 4.57 4.39 4.19 .180 .173 .165 a overall height 1.27 .050 p pitch 68 n number of pins max nom min max nom min dimension limits millimeters inches* units a2 c e2 2 d d1 n #leads=n1 e e1 1 p b a3 a b1 32 d2 68 a1 .145 .153 .160 3.68 3.87 4.06 .028 .035 0.71 0.89 ch1 x 45 ch2 x 45 * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010 ? (0.254mm) per side. jedec equivalent: mo-047 drawing no. c04-093 significant characteristic
? 2001 microchip technology inc. advance information ds39541a-page 303 PIC18C601/801 appendix a: data sheet revision history revision a this is a new data sheet. appendix b: device differences the differences between the PIC18C601/801 devices listed in this data sheet are shown in table b-1. table b-1: device differences feature PIC18C601 pic18c801 maximum external program memory (bytes) 256k 2m data memory (bytes) 1.5k 1.5k a/d channels 8 12 package types tqfp 64-pin 80-pin plcc 68-pin 84-pin
PIC18C601/801 ds39541a-page 304 advance information ? 2001 microchip technology inc. appendix c: device migrations this section is intended to describe the functional and electrical specification differences when migrating between functionally similar devices (such as from a pic16c74a to a pic16c74b). not applicable appendix d: migrating from other picmicro devices this discusses some of the issues in migrating from other picmicro devices to the pic18cxxx family of devices. d.1 pic16cxxx to pic18cxxx see application note an716. d.2 pic17cxxx to pic18cxxx see application note an726.
? 2001 microchip technology inc. advance information ds39541a-page 305 PIC18C601/801 appendix e: development tool version requirements this lists the minimum requirements (software/ firmware) of the specified development tool to support the devices listed in this data sheet. mplab ? ide: tbd mplab ? simulator: tbd mplab ? ice 3000: PIC18C601/801 processor module: part number - tbd PIC18C601/801 device adapter: socket part number 64-pin tqfp tbd 68-pin plcc tbd 80-pin tqfp tbd 84-pin plcc tbd mplab ? icd: tbd pro mate ? ii: tbd picstart ? plus: tbd mpasm tm assembler: tbd mplab ? c18 c compiler: tbd note: please read all associated readme.txt files that are supplied with the develop- ment tools. these "read me" files will dis- cuss product support and any known limitations.
PIC18C601/801 ds39541a-page 306 advance information ? 2001 microchip technology inc. notes:
? 2001 microchip technology inc. advance information ds39541a-page 307 PIC18C601/801 index a a/d ................................................................................... 193 a/d converter flag (adif bit) ................................. 195 a/d converter interrupt, configuring ....................... 197 adcon0 register .......................................... 193 , 195 adcon1 register .......................................... 193 , 194 adcon2 register ................................................... 193 adres register ............................................. 193 , 195 analog port pins, configuring ................................. 199 associated registers ............................................... 201 block diagram ......................................................... 196 block diagram, analog input model ........................ 197 configuring the module ........................................... 197 conversion clock (t ad ) ........................................... 199 conversion status (go/done bit) .......................... 195 conversions ............................................................. 200 converter characteristics ............................... 272 , 292 effects of a reset .................................................. 206 equations acquisition time .............................................. 198 minimum charging time ................................. 198 operation during sleep ......................................... 206 sampling requirements .......................................... 198 sampling time ......................................................... 198 special event trigger (ccp) .......................... 144 , 200 timing diagram ....................................................... 293 absolute maximum ratings ............................................. 265 access bank ...................................................................... 58 adcon0 register ........................................................... 193 go/done bit .......................................................... 195 registers adcon2 (a/d control 2) ................................. 195 adcon1 register .................................................. 193 , 194 adcon2 register ........................................................... 193 addlw ............................................................................ 221 addwf ............................................................................ 221 addwfc ......................................................................... 222 adres register ..................................................... 193 , 195 aks .................................................................................. 167 analog-to-digital converter. see a/d andlw ............................................................................ 222 andwf ............................................................................ 223 assembler mpasm assembler ................................................. 259 b bank select register ......................................................... 58 baud rate generator ....................................................... 164 associated registers ............................................... 179 bc .................................................................................... 223 bcf .................................................................................. 224 bf .................................................................................... 167 block diagram ................................................................. 119 block diagrams a/d ........................................................................... 196 baud rate generator .............................................. 164 capture mode operation ......................................... 143 compare mode operation ....................................... 144 interrupt logic ............................................................ 90 low voltage detect ................................................. 203 mssp i 2 c mode ......................................................... 159 spi mode ......................................................... 153 on-chip reset circuit, simplified .............................. 29 phase lock loop ...................................................... 23 porta ra3:ra0 and ra5 pins .................................. 103 ra4/t0cki pin ................................................ 104 portb rb3 pin ........................................................... 106 rb3:rb0 port pins .......................................... 106 rb7:rb4 port pins .......................................... 105 portc .................................................................... 108 portd i/o mode ......................................................... 110 system bus mode ........................................... 111 portd (in i/o port mode) ...................................... 124 porte i/o mode ......................................................... 113 system bus mode ........................................... 114 portf rf2:rf0 pins .................................................. 116 rf5:rf3 pins .................................................. 117 rf7:rf6 pins .................................................. 117 portg i/o mode ......................................................... 119 system bus mode ........................................... 120 porth rh3:rh0 pins (i/o mode) ............................... 121 rh3:rh0 pins (system bus mode) ................ 122 rh7:rh4 pins ................................................. 121 portj i/o mode ......................................................... 124 system bus mode ........................................... 125 simplified pwm diagram ........................................ 146 ssp (spi mode) ...................................................... 153 timer0 16-bit mode ..................................................... 128 8-bit mode ....................................................... 128 timer1 ..................................................................... 131 16-bit r/w mode ............................................. 132 timer2 ..................................................................... 136 timer3 ..................................................................... 138 16-bit r/w mode ............................................. 138 usart asynchronous receive ................................... 185 asynchronous transmit .................................. 183 watchdog timer ...................................................... 211 bn ................................................................................... 224 bnc ................................................................................. 225 bnn ................................................................................. 225 bnov .............................................................................. 226 bnz ................................................................................. 226 bov ................................................................................. 229 bra ................................................................................. 227 brg ................................................................................. 164 bsf ................................................................................. 227 bsr. see bank select register. btfsc ............................................................................. 228 btfss ............................................................................. 228 btg ................................................................................. 229 bus .................................................................................. 176 bus collision during a restart condition ................... 175 bus collision during a start condition ........................ 173 bus collision during a stop condition .......................... 176 bz .................................................................................... 230
PIC18C601/801 ds39541a-page 308 advance information ? 2001 microchip technology inc. c call ................................................................................ 230 capture (ccp module) .................................................... 142 block diagram ......................................................... 143 ccp pin configuration ............................................. 142 ccpr1h:ccpr1l registers ................................... 142 changing between capture prescalers ................... 143 software interrupt .................................................... 143 timer1 mode selection ............................................ 142 capture/compare/pwm (ccp) ....................................... 141 capture mode. see capture ccp1 ....................................................................... 142 ccpr1h register ........................................... 142 ccpr1l register ............................................ 142 ccp2 ....................................................................... 142 ccpr2h register ........................................... 142 ccpr2l register ............................................ 142 compare mode. see compare interaction of two ccp modules ............................. 142 pwm mode. see pwm registers associated with capture and compare ........................................... 145 timer resources ..................................................... 142 timing diagram ....................................................... 282 chip select chip select 2 (cs2) ................................................... 71 chip select i/o (csio) ...................................................... 71 chip selects chip select 1 (cs1) ................................................... 71 clocking scheme ............................................................... 46 clrf ............................................................................... 231 clrwdt ......................................................................... 231 code examples ............................................................... 154 changing between capture prescalers ................... 143 clearing ram using indirect addressing .................. 59 combination unlock (macro) ..................................... 51 combination unlock (subroutine) .............................. 50 fast register stack ................................................... 45 initializing porta .................................................... 103 initializing portb .................................................... 105 initializing portc ................................................... 108 initializing portd ................................................... 110 initializing porte .................................................... 113 initializing portf .................................................... 116 initializing portg ................................................... 119 initializing porth ................................................... 121 initializing portj .................................................... 124 programming chip select signals ........................... 116 saving status, wreg and bsr registers .......... 101 table read ................................................................ 75 table write ................................................................ 77 comf .............................................................................. 232 compare (ccp module) .................................................. 144 block diagram ......................................................... 144 ccp pin configuration ............................................. 144 ccpr1h:ccpr1l registers ................................... 144 software interrupt .................................................... 144 special event trigger .................... 133 , 139 , 144 , 200 timer1 mode selection ............................................ 144 configuration address map, example ............................... 71 configuration bits ............................................................ 207 table ........................................................................ 207 context saving during interrupts ..................................... 101 cpfseq .......................................................................... 232 cpfsgt .......................................................................... 233 cpfslt ........................................................................... 233 d data memory ..................................................................... 49 general purpose registers ....................................... 49 special function registers ........................................ 49 data memory map program bit not set .................................................. 51 program bit set ......................................................... 52 daw ................................................................................ 234 dc and ac characteristics graphs and tables .............. 295 dcfsnz .......................................................................... 235 decf ............................................................................... 234 decfsz .......................................................................... 235 development support ...................................................... 259 development tool version requirements ....................... 305 device differences .......................................................... 303 device migrations ............................................................ 304 direct addressing .............................................................. 60 e electrical characteristics ................................................. 265 errata ................................................................................... 7 external wait cycles ......................................................... 72 f fast register stack ........................................................... 45 firmware instructions ...................................................... 215 g general call address sequence ..................................... 162 general call address support ......................................... 162 goto .............................................................................. 236 i i/o mode .......................................................................... 119 i/o ports .......................................................................... 103 i 2 c (ssp module) ............................................................ 159 ack pulse .......................................................159 , 160 addressing .............................................................. 160 block diagram ......................................................... 159 read/write bit information (r/w bit) ....................... 160 reception ................................................................ 160 serial clock (rc3/sck/scl) .................................. 160 slave mode ............................................................. 159 timing diagram, data ............................................. 287 timing diagram, start/stop bits ....................... 287 transmission ........................................................... 160 i 2 c master mode reception ............................................ 167 i 2 c master mode restart condition ........................... 166 i 2 c module acknowledge sequence timing .............................. 170 baud rate generator .............................................. 164 block diagram ................................................. 164 brg reset due to sda collision ............................ 174 brg timing ............................................................. 165 bus collision acknowledge ................................................... 172 restart condition ....................................... 175 restart condition timing (case1) .............. 175 restart condition timing (case2) .............. 175 start condition ............................................ 173 start condition timing ........................173 , 174 stop condition .............................................. 176 stop condition timing (case1) ..................... 176 stop condition timing (case2) ..................... 176 transmit timing .............................................. 172 bus collision timing ................................................ 172
? 2001 microchip technology inc. advance information ds39541a-page 309 PIC18C601/801 clock arbitration ...................................................... 171 clock arbitration timing (master transmit) ............. 171 general call address support ................................. 162 master mode 7-bit reception timing ....................... 169 master mode operation ........................................... 164 master mode start condition ............................... 165 master mode transmission ..................................... 167 master mode transmit sequence ........................... 164 multi-master mode ................................................... 172 repeated start condition timing ........................ 166 stop condition receive or transmit timing .......... 170 stop condition timing ........................................... 170 waveforms for 7-bit reception ................................ 161 waveforms for 7-bit transmission ........................... 161 icepic in-circuit emulator .............................................. 260 incf ................................................................................ 236 incfsz ............................................................................ 237 in-circuit serial programming (icsp) .............................. 207 indirect addressing ............................................................ 60 fsr register ............................................................. 59 infsnz ............................................................................ 237 initialization conditions for all registers ............................ 34 instruction cycle ................................................................ 46 instruction flow/pipelining ................................................. 47 instruction format ............................................................ 217 instruction set .................................................................. 215 addlw .................................................................... 221 addwf ................................................................... 221 addwfc ................................................................. 222 andlw .................................................................... 222 andwf ................................................................... 223 bc ............................................................................ 223 bcf ......................................................................... 224 bn ............................................................................ 224 bnc ......................................................................... 225 bnn ......................................................................... 225 bnov ...................................................................... 226 bnz ......................................................................... 226 bov ......................................................................... 229 bra ......................................................................... 227 bsf .......................................................................... 227 btfsc ..................................................................... 228 btfss ..................................................................... 228 btg ......................................................................... 229 bz ............................................................................ 230 call ........................................................................ 230 clrf ....................................................................... 231 clrwdt ................................................................. 231 comf ...................................................................... 232 cpfseq .................................................................. 232 cpfsgt .................................................................. 233 cpfslt ................................................................... 233 daw ........................................................................ 234 dcfsnz .................................................................. 235 decf ....................................................................... 234 decfsz .................................................................. 235 goto ...................................................................... 236 incf ........................................................................ 236 incfsz .................................................................... 237 infsnz .................................................................... 237 iorlw ..................................................................... 238 iorwf ..................................................................... 238 lfsr ....................................................................... 239 movf ...................................................................... 239 movff .................................................................... 240 movlb .................................................................... 240 movlw ................................................................... 241 movwf .................................................................. 241 mullw ................................................................... 242 mulwf ................................................................... 242 negf ...................................................................... 243 nop ........................................................................ 243 pop ......................................................................... 244 push ...................................................................... 244 rcall ..................................................................... 245 reset .................................................................... 245 retfie ................................................................... 246 retlw .................................................................... 246 return ................................................................. 247 rlcf ....................................................................... 247 rlncf .................................................................... 248 rrcf ...................................................................... 248 rrncf .................................................................... 249 setf ....................................................................... 249 sleep ..................................................................... 250 subfwb .........................................................250 , 251 sublw ................................................................... 251 subwf ................................................................... 252 subwfb ................................................................. 253 swapf ................................................................... 254 tblrd .................................................................... 255 tblwt .................................................................... 256 tstfsz ................................................................... 257 xorlw ................................................................... 257 xorwf ................................................................... 258 instruction set, summary ................................................ 218 int interrupt (rb0/int). see interrupt sources intcon register rbif bit ................................................................... 105 inter-integrated circuit. see i 2 c interrupt control registers ................................................ 91 intcon register ...................................................... 91 intcon2 register .................................................... 92 intcon3 register .................................................... 93 ipr registers ............................................................ 99 pie registers ............................................................ 97 pir registers ............................................................ 95 rcon register ......................................................... 94 interrupt sources .......................................................89 , 207 a/d conversion complete ....................................... 197 capture complete (ccp) ........................................ 143 compare complete (ccp) ...................................... 144 interrupt-on-change (rb7:rb4) ............................. 105 rb0/int pin, external ............................................. 101 ssp receive/transmit complete ............................ 149 tmr0 overflow ....................................................... 129 tmr1 overflow ...............................................130 , 133 tmr2 to pr2 match ................................................ 136 tmr2 to pr2 match (pwm) ...........................135 , 146 tmr3 overflow ...............................................137 , 139 usart receive/transmit complete ....................... 177 interrupts, enable bits ccp1 enable (ccp1ie bit) ..................................... 143 interrupts, flag bits a/d converter flag (adif bit) ................................. 195 ccp1 flag (ccp1if bit) ........................ 142 , 143 , 144 interrupt-on-change (rb7:rb4) flag (rbif bit) ................................................ 105 iorlw ............................................................................. 238 iorwf ............................................................................ 238
PIC18C601/801 ds39541a-page 310 advance information ? 2001 microchip technology inc. k k ee l oq evaluation and programming tools ................... 262 l lfsr ................................................................................ 239 loading the sspbuf (sspsr) registers ....................... 154 low voltage detect .......................................................... 203 block diagram ......................................................... 203 lvdcon register ................................................... 204 lvd. see low voltage detect. m memcom. see memory control register memory .............................................................................. 39 memory control register (memcom) ............................... 63 memory organization ........................................................ 39 data memory ............................................................. 49 program memory ....................................................... 39 migrating from other picmicro devices ........................... 304 movf .............................................................................. 239 movff ............................................................................ 240 movlb ............................................................................ 240 movlw ........................................................................... 241 movwf ........................................................................... 241 mplab c17 and mplab c18 c compilers .................... 259 mplab icd in-circuit debugger ..................................... 261 mplab ice high performance universal in-circuit emulator with mplab ide ....................... 260 mplab integrated development environment software ............................................. 259 mplink object linker/mplib object librarian ............... 260 mullw ............................................................................ 242 multi-master mode ........................................................... 172 multiplication algorithm 16 x 16 signed ........................................................... 86 16 x 16 unsigned ....................................................... 86 multiply examples 16 x 16 signed routine ............................................. 87 16 x 16 unsigned routine ......................................... 86 8 x 8 signed routine ................................................. 86 8 x 8 unsigned routine ............................................. 86 mulwf ............................................................................ 242 n negf ............................................................................... 243 nop ................................................................................. 243 o on-chip reset circuit ........................................................ 29 option_reg register ..................................................... 62 ps2:ps0 bits ........................................................... 129 psa bit .................................................................... 129 t0cs bit .................................................................. 129 t0se bit ................................................................... 129 osccon register ............................................................. 25 oscillator configuration ................................................... 207 oscillator configurations .................................................... 21 hs .............................................................................. 21 lp .............................................................................. 21 rc ....................................................................... 21 , 22 oscillator, timer1 ............................................130 , 133 , 137 oscillator, timer3 ............................................................. 139 oscillator, wdt ................................................................ 210 p packaging ........................................................................ 297 phase lock loop block diagram ........................................................... 23 time-out .................................................................... 30 picdem 1 low cost picmicro demonstration board .............................................. 261 picdem 17 demonstration board .................................. 262 picdem 2 low cost pic16cxx demonstration board .............................................. 261 picdem 3 low cost pic16cxxx demonstration board .............................................. 262 picstart plus entry level development programmer ...................................... 261 pin functions a vdd .......................................................................... 20 a vss .......................................................................... 20 mclr /v pp ................................................................. 12 osc1/clki ................................................................ 12 osc2/clko .............................................................. 12 ra0/an0 ................................................................... 13 ra1/an1 ................................................................... 13 ra2/an2/v ref - ......................................................... 13 ra3/an3/v ref + ........................................................ 13 ra4/t0cki ................................................................ 13 ra5/an4/ss /lvdin .................................................. 13 rb0/int0 ................................................................... 14 rb1/int1 ................................................................... 14 rb2/int2 ................................................................... 14 rb3/int3 ................................................................... 14 rb4 ........................................................................... 14 rb5 ........................................................................... 14 rb6 ........................................................................... 14 rb7 ........................................................................... 14 rc0/t1oso/t1cki ................................................... 15 rc1/t1osi ................................................................ 15 rc2/ccp1 ................................................................. 15 rc3/sck/scl ........................................................... 15 rc4/sdi/sda ............................................................ 15 rc5/sdo .................................................................. 15 rc6/tx/ck ................................................................ 15 rc7/rx/dt ............................................................... 15 rd0/ad0 ................................................................... 16 rd0/psp0 ................................................................. 16 rd1/ad1 ................................................................... 16 rd2/ad2 ................................................................... 16 rd3/ad3 ................................................................... 16 rd4/ad4 ................................................................... 16 rd5/ad5 ................................................................... 16 rd6/ad6 ................................................................... 16 rd7/ad7 ................................................................... 16 re0/ale .................................................................... 17 re1/oe ..................................................................... 17 re2/cs ........................................................ 17 , 18 , 19 re2/wrl .................................................................. 17 re3/wrh .................................................................. 17 re4 ........................................................................... 17 re5 ........................................................................... 17 re6 ........................................................................... 17 re7/ccp2 ................................................................. 17 rf0/an5 .................................................................... 18 rf1/an6 .................................................................... 18 rf2/an7 .................................................................... 18 rf3/an8 .................................................................... 18 rf4/an9 .................................................................... 18
? 2001 microchip technology inc. advance information ds39541a-page 311 PIC18C601/801 rf5/an10 .................................................................. 18 rf6/an11 .................................................................. 18 rf7 ............................................................................ 18 rg0/cantx1 ............................................................ 19 rg1/cantx2 ............................................................ 19 rg2/canrx .............................................................. 19 rg3 ........................................................................... 19 rg4 ........................................................................... 19 rh1/a17 .................................................................... 19 rh2/a18 .................................................................... 19 rh3/a19 .................................................................... 19 rh4/an12 ................................................................. 19 rh5/an13 ................................................................. 19 rh6/an14 ................................................................. 19 rh7/an15 ................................................................. 19 rj0/ad8 .................................................................... 20 rj1/ad9 .................................................................... 20 rj2/ad10 .................................................................. 20 rj3/ad11 .................................................................. 20 rj4/ad12 .................................................................. 20 rj5/ad13 .................................................................. 20 rj6/ad14 .................................................................. 20 rj7/ad15 .................................................................. 20 v dd ............................................................................ 20 v ss ............................................................................ 20 pop ................................................................................. 244 por. see power-on reset porta associated registers ............................................... 104 block diagram ra3:ra0 and ra5 pins ................................... 103 ra4/t0cki pin ................................................ 104 functions ................................................................. 104 initialization .............................................................. 103 porta register ...................................................... 103 trisa register ........................................................ 103 portb associated registers ............................................... 107 block diagram rb3 pin ........................................................... 106 rb3:rb0 port pins .......................................... 106 rb7:rb4 port pins .......................................... 105 functions ................................................................. 107 initialization .............................................................. 105 portb register ...................................................... 105 rb0/int pin, external ............................................. 101 rb7:rb4 interrupt-on-change flag (rbif bit) ....... 105 trisb register ........................................................ 105 portc associated registers ............................................... 109 block diagram ......................................................... 108 functions ................................................................. 109 initialization .............................................................. 108 portc register ...................................................... 108 rc3/sck/scl pin ................................................... 160 rc7/rx/dt pin ....................................................... 179 trisc register .............................................. 108 , 177 portd associated registers ............................................... 112 block diagram i/o mode .......................................................... 110 system bus mode ........................................... 111 functions ................................................................. 112 initialization .............................................................. 110 portd register ...................................................... 110 trisd register ....................................................... 110 porte associated registers .............................................. 115 block diagram i/o mode ......................................................... 113 system bus mode ........................................... 114 functions ................................................................. 115 initialization ............................................................. 113 porte register ..................................................... 113 trise register ....................................................... 113 portf associated registers .............................................. 118 block diagram rf2:rf0 pins .................................................. 116 rf5:rf3 pins .................................................. 117 rf7:rf6 pins .................................................. 117 functions ................................................................. 118 initialization ............................................................. 116 portf register ...................................................... 116 trisf ...................................................................... 116 portg ............................................................................ 119 associated registers .............................................. 120 block diagram system bus mode ........................................... 120 functions ................................................................. 120 initialization ............................................................. 119 portg register ..................................................... 119 trisg ..................................................................... 119 porth associated registers .............................................. 123 block diagram .................................................121 , 122 functions ................................................................. 123 initialization ............................................................. 121 porth register ..................................................... 121 trish ..................................................................... 121 portj associated registers .............................................. 126 block diagram i/o mode ......................................................... 124 system bus mode ........................................... 125 functions ................................................................. 126 initialization ............................................................. 124 portj register ...................................................... 124 trisj ...................................................................... 124 postscaler, wdt assignment (psa bit) .............................................. 129 rate select (ps2:ps0 bits) ..................................... 129 switching between timer0 and wdt ..................... 129 power-down mode. see sleep power-on reset (por) .............................................30 , 207 oscillator start-up timer (ost) ........................30 , 207 power-up timer (pwrt) ...................................30 , 207 time-out sequence ................................................... 30 time-out sequence on power-up .......................32 , 33 timing diagram ....................................................... 280 prescaler, capture .......................................................... 143 prescaler, timer0 ............................................................ 129 assignment (psa bit) .............................................. 129 rate select (ps2:ps0 bits) ..................................... 129 switching between timer0 and wdt ..................... 129 prescaler, timer1 ............................................................ 131 prescaler, timer2 ............................................................ 146 pro mate ii universal device programmer .................. 261 product identification system .......................................... 317
PIC18C601/801 ds39541a-page 312 advance information ? 2001 microchip technology inc. program counter pcl register ............................................................. 46 pclath register ...................................................... 46 program memory ............................................................... 39 boot loader ............................................................... 43 memory map, PIC18C601 program bit not set ........................................... 40 program bit set ................................................. 41 memory map, pic18c801 program bit not set ........................................... 40 program bit set ................................................. 42 program memory map PIC18C601 ................................................................ 40 program bit set ................................................. 41 pic18c801 ................................................................ 40 program bit set ................................................. 42 programming, device instructions ................................... 215 push ............................................................................... 244 pwm (ccp module) ........................................................ 146 block diagram ......................................................... 146 ccpr1h:ccpr1l registers ................................... 146 duty cycle ............................................................... 146 example frequencies/resolutions .......................... 147 output diagram ....................................................... 146 period ...................................................................... 146 registers associated with pwm .............................. 147 setup for pwm operation ........................................ 147 tmr2 to pr2 match ....................................... 135 , 146 q q clock ............................................................................ 146 r ram. see data memory rcall ............................................................................. 245 rcsta register spen bit .................................................................. 177 reader response ............................................................ 316 register file ....................................................................... 49 register file summary ...................................................... 54 registers adcon0 (a/d control 0) .......................................... 193 adcon1 (a/d control 1) ......................................... 194 ccp1con and ccp2con (ccp control) .............. 141 config1h (configuration register 1 high) ............ 208 config2h (configuration register 2 high) ............ 209 config2l (configuration register 2 low) ............. 208 config4l (configuration register 4 low) ............. 209 csel2 (chip select 2) ............................................... 70 cselio (chip select i/o) .......................................... 70 intcon (interrupt control) ........................................ 91 intcon2 (interrupt control 2) ................................... 92 intcon3 (interrupt control 3) ................................... 93 ipr (interrupt priority) ................................................ 99 lvdcon (lvd control) ........................................... 204 memcon (memory control) ..................................... 63 osccon (oscillator control) .................................... 25 pie (peripheral interrupt enable) ............................... 97 pir (peripheral interrupt request) ............................ 95 pspcon (psp control) ............................................ 50 rcon (register control) ........................................... 94 rcon (reset control) ..................................... 31 , 62 rcsta (receive status and control) ..................... 178 sspcon1 (ssp control 1) ..................................... 151 sspcon2 (ssp control 2) ...................................... 152 sspstat (ssp status) .......................................... 150 status .................................................................... 61 stkptr (stack pointer) ........................................... 44 t0con (timer0 control) ......................................... 127 t1con (timer1 control) ......................................... 130 t2con (timer2 control) ......................................... 135 t3con (timer3 control) ......................................... 137 txsta (transmit status and control) ..................... 177 wdtcon (watchdog timer control) ...................... 210 reset ............................................................. 29 , 207 , 245 timing diagram ....................................................... 280 retfie ............................................................................ 246 retlw ............................................................................ 246 return ......................................................................... 247 revision history .............................................................. 303 rh3:rh0 pins (i/o mode) ............................................... 121 rh3:rh0 pins (system bus mode) ................................ 122 rh7:rh4 pins ................................................................. 121 rlcf ............................................................................... 247 rlncf ............................................................................ 248 rrcf .............................................................................. 248 rrncf ............................................................................ 249 s sales and support ........................................................... 317 sci. see usart sck ................................................................................. 153 sdi .................................................................................. 153 sdo ................................................................................. 153 serial clock, sck ............................................................ 153 serial communication interface. see usart serial data in, sdi ........................................................... 153 serial data out, sdo ...................................................... 153 serial peripheral interface. see spi setf ............................................................................... 249 slave select synchronization .......................................... 156 slave select, ss .............................................................. 153 sleep ............................................................ 207 , 212 , 250 software simulator (mplab sim) ................................... 260 special event trigger. see compare special features of the cpu ........................................... 207 special function register map ......................................... 53 special function registers ................................................ 49 spi associated registers ............................................... 158 master mode ........................................................... 155 serial clock ............................................................. 153 serial data in ........................................................... 153 serial data out ........................................................ 153 slave select ............................................................ 153 spi clock ................................................................. 155 spi mode ................................................................. 153 spi module slave mode ............................................................. 156 slave select synchronization .................................. 156 slave synch timing ................................................. 156 slave timing with cke = 0 ...................................... 157 slave timing with cke = 1 ...................................... 157 ss .................................................................................... 153
? 2001 microchip technology inc. advance information ds39541a-page 313 PIC18C601/801 ssp .................................................................................. 149 block diagram spi mode ......................................................... 153 block diagram (spi mode) ...................................... 153 i 2 c mode. see i 2 c spi mode ................................................................. 153 spi mode. see spi sspbuf .................................................................. 155 sspcon1 ............................................................... 151 sspcon2 ............................................................... 152 sspsr .................................................................... 155 sspstat ................................................................ 150 tmr2 output for clock shift ........................... 135 , 136 ssp module spi master mode ..................................................... 155 spi slave mode ....................................................... 156 sspcon1 register ......................................................... 151 sspcon2 register ......................................................... 152 sspov ............................................................................ 167 sspstat register .......................................................... 150 r/w bit .................................................................... 160 subfwb ................................................................ 250 , 251 sublw ............................................................................ 251 subwf ............................................................................ 252 subwfb ......................................................................... 253 swapf ............................................................................ 254 synchronous serial port. see ssp t table pointer register ....................................................... 74 table read ........................................................................ 75 table read/write control registers .................................. 74 table write ........................................................................ 77 16-bit external 16-bit word write mode ..................................... 81 byte select mode .............................................. 82 byte write mode ................................................ 80 8-bit external ............................................................. 78 table writes long writes ............................................................... 83 tblrd ............................................................................. 255 tblwt ............................................................................. 256 timer0 .............................................................................. 127 associated registers ............................................... 129 block diagram 16-bit mode ...................................................... 128 8-bit mode ........................................................ 128 clock source edge select (t0se bit) ..................... 129 clock source select (t0cs bit) .............................. 129 interrupt ................................................................... 101 overflow interrupt .................................................... 129 prescaler. see prescaler, timer0 t0con register ...................................................... 127 timing diagram ....................................................... 281 timer1 .............................................................................. 130 associated registers ............................................... 134 block diagram ......................................................... 131 16-bit r/w mode .............................................. 132 oscillator ......................................................... 130 , 133 overflow interrupt ........................................... 130 , 133 prescaler. see prescaler, timer1 special event trigger (ccp) ...........................133 , 144 t1con register ...................................................... 130 timing diagram ....................................................... 281 tmr1h register ..................................................... 130 tmr1l register ...................................................... 130 tmr3l register ...................................................... 137 timer2 associated registers .............................................. 136 block diagram ......................................................... 136 postscaler. see postscaler, timer2 pr2 register ...................................................135 , 146 prescaler. see prescaler, timer2 ssp clock shift ...............................................135 , 136 t2con register ...................................................... 135 tmr2 register ........................................................ 135 tmr2 to pr2 match interrupt ................ 135 , 136 , 146 timer3 ............................................................................. 137 associated registers .............................................. 139 block diagram ......................................................... 138 16-bit r/w mode ............................................. 138 oscillator .........................................................137 , 139 overflow interrupt ............................................137 , 139 special event trigger (ccp) ................................... 139 t3con register ...................................................... 137 tmr3h register ..................................................... 137 timing diagrams acknowledge sequence timing .............................. 170 baud rate generator with clock arbitration ........... 165 brg reset due to sda collision ........................... 174 bus collision start condition timing ................................ 173 bus collision during a restart condition (case 1) .................................................. 175 bus collision during a restart condition (case 2) .................................................. 175 bus collision during a start condition (scl = 0) ................................................. 174 bus collision during a stop condition .................. 176 bus collision for transmit and acknowledge .......... 172 i 2 c bus data ........................................................... 289 i 2 c master mode first start bit timing ............... 165 i 2 c master mode reception timing ........................ 169 i 2 c master mode transmission timing ................... 168 master mode transmit clock arbitration ................. 171 repeated start condition .................................... 166 slave synchronization ............................................. 156 slow rise time ......................................................... 33 spi mode timing (master mode) spi mode master mode timing diagram ......................... 155 spi mode timing (slave mode with cke = 0) ........ 157 spi mode timing (slave mode with cke = 1) ........ 157 stop condition receive or transmit ..................... 170 time-out sequence on power-up ............................. 32 usart asynchronous master transmission .......... 184 usart asynchronous reception ........................... 186 usart synchronous reception ............................. 189 usart synchronous transmission ........................ 188 wake-up from sleep via interrupt ......................... 213
PIC18C601/801 ds39541a-page 314 advance information ? 2001 microchip technology inc. timing diagrams and specifications ............................... 275 a/d conversion ........................................................ 293 capture/compare/pwm (ccp) ............................... 282 clkout and i/o ..................................................... 276 external clock .......................................................... 275 i 2 c bus data ............................................................ 287 i 2 c bus start/stop bits ...................................... 287 oscillator start-up timer (ost) ............................... 280 power-up timer (pwrt) ......................................... 280 reset ..................................................................... 280 timer0 and timer1 .................................................. 281 usart synchronous receive (master/slave) ......................................... 291 usart synchronous transmission (master/slave) ......................................... 291 watchdog timer (wdt) ........................................... 280 trise register ................................................................ 113 tstfsz ........................................................................... 257 two-word instructions ....................................................... 48 txsta register ............................................................... 177 brgh bit ................................................................. 179 u universal synchronous asynchronous receiver transmitter. see usart usart ............................................................................. 177 asynchronous mode ................................................ 183 master transmission ....................................... 184 receive block diagram ................................... 185 reception ........................................................ 186 registers associated with reception .............. 186 registers associated with transmission ......... 184 transmit block diagram .................................. 183 baud rate generator (brg) ................................... 179 baud rate error, calculating ........................... 179 baud rate formula ......................................... 179 high baud rate select (brgh bit) ................. 179 sampling .......................................................... 179 serial port enable (spen bit) ................................. 177 synchronous master mode ...................................... 187 reception ........................................................ 189 registers associated with reception .............. 189 registers associated with transmission ......... 187 timing diagram, synchronous receive ..................... 291 timing diagram, synchronous transmission ............. 291 transmission ................................................... 188 synchronous slave mode ........................................ 190 registers associated with reception .............. 191 registers associated with transmission ......... 190 w wake-up from sleep .............................................207 , 212 timing diagram ....................................................... 213 watchdog timer (wdt) ..........................................207 , 210 associated registers ............................................... 211 block diagram ......................................................... 211 postscaler. see postscaler, wdt programming considerations .................................. 210 rc oscillator ........................................................... 210 time-out period ....................................................... 210 timing diagram ....................................................... 280 wdtcon register .................................................. 210 waveform for general call address sequence .............. 162 wcol ............................................................. 165 , 167 , 170 wcol status flag .......................................................... 165 worldwide sales and service .......................................... 318 www, on-line support ..............................................7 , 315 x xorlw ........................................................................... 257 xorwf ........................................................................... 258
? 2001 microchip technology inc. advance information ds39541a-page 315 PIC18C601/801 systems information and upgrade hot line the systems information and upgrade line provides system users a listing of the latest versions of all of microchip ? s development systems software products. plus, this line provides information on how customers can receive any currently available upgrade kits.the hot line numbers are: 1-800-755-2345 for u.s. and most of canada, and 1-480-792-7302 for the rest of the world. trademarks: the microchip name, logo, pic, picmicro, picmaster, picstart, pro mate, k ee l oq , seeval, mplab and the embedded control solutions company are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. total endurance, icsp, in-circuit serial programming, filterlab, mxdev, microid, flex rom, fuzzy lab, mpasm, mplink, mplib, picdem, icepic and migratable memory are trademarks and sqtp is a service mark of microchip in the u.s.a. all other trademarks mentioned herein are the property of their respective companies. on-line support microchip provides on-line support on the microchip world wide web (www) site. the web site is used by microchip as a means to make files and information easily available to customers. to view the site, the user must have access to the internet and a web browser, such as netscape or microsoft explorer. files are also available for ftp download from our ftp site. connecting to the microchip internet web site the microchip web site is available by using your favorite internet browser to attach to: www.microchip.com the file transfer site is available by using an ftp ser- vice to connect to: ftp://ftp.microchip.com the web site and file transfer site provide a variety of services. users may download files for the latest development tools, data sheets, application notes, user ? s guides, articles and sample programs. a vari- ety of microchip specific business information is also available, including listings of microchip sales offices, distributors and factory representatives. other data available for consideration is: latest microchip press releases technical support section with frequently asked questions design tips device errata job postings microchip consultant program member listing links to other useful web sites related to microchip products conferences for products, development systems, technical information and more listing of seminars and events 001024
PIC18C601/801 ds39541a-page 316 advance information ? 2001 microchip technology inc. reader response it is our intention to provide you with the best documentation possible to ensure successful use of your microchip prod- uct. if you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please fax your comments to the technical publications manager at (480) 792-4150. please list the following information, and use this outline to provide us with your comments about this data sheet. 1. what are the best features of this document? 2. how does this document meet your hardware and software development needs? 3. do you find the organization of this data sheet easy to follow? if not, why? 4. what additions to the data sheet do you think would enhance the structure and subject? 5. what deletions from the data sheet could be made without affecting the overall usefulness? 6. is there any incorrect or misleading information (what and where)? 7. how would you improve this document? 8. how would you improve our software, systems, and silicon products? to : technical publications manager re: reader response total pages sent from: name company address city / state / zip / country telephone: (_______) _________ - _________ application (optional): would you like a reply? y n device: literature number: questions: fax: (______) _________ - _________ ds39541a PIC18C601/801
? 2001 microchip technology inc. advance information ds39541a-page 317 PIC18C601/801 product identification system to order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. sales and support data sheets products supported by a preliminary data sheet may have an errata sheet describing minor operational differences and recom- mended workarounds. to determine if an errata sheet exists for a particular device, please contact one of the following: 1. your local microchip sales office 2. the microchip corporate literature center u.s. fax: (480) 792-7277 3. the microchip worldwide site (www.microchip.com) please specify which device, revision of silicon and data sheet (include literature #) you are using. new customer notification system register on our web site (www.microchip.com/cn) to receive the most current information on our products. part no. x /xx xxx pattern package temperature range device device PIC18C601/801 (1) , PIC18C601/801t (2) : v dd range, 4.2v to 5.5v pic18lc601/801 (1) , pic18lc601/801t (2) v dd range, 2.5v to 5.5v temperature range i = -40 c to +70 c (industrial) e= -40 c to +125 c (extended) package pt = tqfp l=plcc pattern qtp, sqtp, rom code (factory specified) or special requirements. blank for otp and windowed devices. examples: a) pic18lc601 - i/l = industrial temp., plcc package, extended v dd limits, 16-bit data bus. b) pic18lc801 - e/pt = extended temp., tqfp package, extended v dd limits, 16-bit data bus. note 1: c = standard voltage range lc = wide voltage range 2: t = in tape and reel (both plcc and tqfp packages)
PIC18C601/801 ds39541a-page 318 advance information ? 2001 microchip technology inc. notes:
? 2001 microchip technology inc. advance information ds39541a-page 319 PIC18C601/801 notes:
information contained in this publication regarding device applications and the like is intended through suggestion only and ma y be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. no representation or warrant y is given and no liability is assumed by microchip technology incorporated with respect to the accuracy or use of such information, or infringement of patent s or other intellectual property rights arising from such use or otherwise. use of microchip?s products as critical components in life support systems is not authorized except with express written approval by microchip. no licenses are conveyed, implicitly or otherwise, except as maybe explicitly expressed herein, under any intellec- tual property rights. the microchip logo and name are registered trademarks of microchip technology inc. in the u.s.a. and othe r countries. all rights reserved. all other trademarks mentioned herein are the property of their respective companies. ds39541a-page 320 advance information ? 2001 microchip technology inc. all rights reserved. ? 2001 microchip technology incorporated. printed in the usa. 1/01 printed on recycled paper. americas corporate office 2355 west chandler blvd. chandler, az 85224-6199 tel: 480-792-7200 fax: 480-792-7277 technical support: 480-792-7627 web address: http://www.microchip.com rocky mountain 2355 west chandler blvd. chandler, az 85224-6199 tel: 480-792-7966 fax: 480-792-7456 atlanta 500 sugar mill road, suite 200b atlanta, ga 30350 tel: 770-640-0034 fax: 770-640-0307 boston 2 lan drive, suite 120 westford, ma 01886 tel: 978-692-3848 fax: 978-692-3821 chicago 333 pierce road, suite 180 itasca, il 60143 tel: 630-285-0071 fax: 630-285-0075 dallas 4570 westgrove drive, suite 160 addison, tx 75001 tel: 972-818-7423 fax: 972-818-2924 dayton two prestige place, suite 130 miamisburg, oh 45342 tel: 937-291-1654 fax: 937-291-9175 detroit tri-atria office building 32255 northwestern highway, suite 190 farmington hills, mi 48334 tel: 248-538-2250 fax: 248-538-2260 los angeles 18201 von karman, suite 1090 irvine, ca 92612 tel: 949-263-1888 fax: 949-263-1338 new york 150 motor parkway, suite 202 hauppauge, ny 11788 tel: 631-273-5305 fax: 631-273-5335 san jose microchip technology inc. 2107 north first street, suite 590 san jose, ca 95131 tel: 408-436-7950 fax: 408-436-7955 toronto 6285 northam drive, suite 108 mississauga, ontario l4v 1x5, canada tel: 905-673-0699 fax: 905-673-6509 asia/pacific china - beijing microchip technology beijing office unit 915 new china hong kong manhattan bldg. no. 6 chaoyangmen beidajie beijing, 100027, no. china tel: 86-10-85282100 fax: 86-10-85282104 china - shanghai microchip technology shanghai office room 701, bldg. b far east international plaza no. 317 xian xia road shanghai, 200051 tel: 86-21-6275-5700 fax: 86-21-6275-5060 hong kong microchip asia pacific rm 2101, tower 2, metroplaza 223 hing fong road kwai fong, n.t., hong kong tel: 852-2401-1200 fax: 852-2401-3431 india microchip technology inc. india liaison office divyasree chambers 1 floor, wing a (a3/a4) no. 11, o ? shaugnessey road bangalore, 560 025, india tel: 91-80-2290061 fax: 91-80-2290062 japan microchip technology intl. inc. benex s-1 6f 3-18-20, shinyokohama kohoku-ku, yokohama-shi kanagawa, 222-0033, japan tel: 81-45-471- 6166 fax: 81-45-471-6122 korea microchip technology korea 168-1, youngbo bldg. 3 floor samsung-dong, kangnam-ku seoul, korea tel: 82-2-554-7200 fax: 82-2-558-5934 asia/pacific (continued) singapore microchip technology singapore pte ltd. 200 middle road #07-02 prime centre singapore, 188980 tel: 65-334-8870 fax: 65-334-8850 taiwan microchip technology taiwan 11f-3, no. 207 tung hua north road taipei, 105, taiwan tel: 886-2-2717-7175 fax: 886-2-2545-0139 europe denmark microchip technology denmark aps regus business centre lautrup hoj 1-3 ballerup dk-2750 denmark tel: 45 4420 9895 fax: 45 4420 9910 france arizona microchip technology sarl parc d ? activite du moulin de massy 43 rue du saule trapu batiment a - ler etage 91300 massy, france tel: 33-1-69-53-63-20 fax: 33-1-69-30-90-79 germany arizona microchip technology gmbh gustav-heinemann ring 125 d-81739 munich, germany tel: 49-89-627-144 0 fax: 49-89-627-144-44 italy arizona microchip technology srl centro direzionale colleoni palazzo taurus 1 v. le colleoni 1 20041 agrate brianza milan, italy tel: 39-039-65791-1 fax: 39-039-6899883 united kingdom arizona microchip technology ltd. 505 eskdale road winnersh triangle wokingham berkshire, england rg41 5tu tel: 44 118 921 5869 fax: 44-118 921-5820 10/01/00 w orldwide s ales and s ervice microchip received qs-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona in july 1999. the company?s quality system processes and procedures are qs-9000 compliant for its picmicro ? 8-bit mcus, k ee l oq ? code hopping devices, serial eeproms and microperipheral products. in addition, microchip ? s quality system for the design and manufacture of development systems is iso 9001 certified.

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